prio/Paper/Paper.thy
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(*<*)
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theory Paper
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imports "../CpsG" "../ExtGG" "~~/src/HOL/Library/LaTeXsugar"
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begin
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ML {*
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  open Printer;
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  show_question_marks_default := false;
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  *}
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notation (latex output)
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  Cons ("_::_" [78,77] 73) and
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  vt ("valid'_state") and
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  runing ("running") and
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  birthtime ("last'_set") and
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  If  ("(\<^raw:\textrm{>if\<^raw:}> (_)/ \<^raw:\textrm{>then\<^raw:}> (_)/ \<^raw:\textrm{>else\<^raw:}> (_))" 10) and
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  Prc ("'(_, _')") and
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  holding ("holds") and
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  waiting ("waits") and
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  Th ("T") and
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  Cs ("C") and
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  readys ("ready") and
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  depend ("RAG") and 
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  preced ("prec") and
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  cpreced ("cprec") and
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  dependents ("dependants") and
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  cp ("cprec") and
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  holdents ("resources") and
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  original_priority ("priority") and
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  DUMMY  ("\<^raw:\mbox{$\_\!\_$}>")
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(*>*)
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section {* Introduction *}
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text {*
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  Many real-time systems need to support threads involving priorities and
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  locking of resources. Locking of resources ensures mutual exclusion
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  when accessing shared data or devices that cannot be
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  preempted. Priorities allow scheduling of threads that need to
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  finish their work within deadlines.  Unfortunately, both features
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  can interact in subtle ways leading to a problem, called
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  \emph{Priority Inversion}. Suppose three threads having priorities
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  $H$(igh), $M$(edium) and $L$(ow). We would expect that the thread
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  $H$ blocks any other thread with lower priority and itself cannot
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  be blocked by any thread with lower priority. Alas, in a naive
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  implementation of resource looking and priorities this property can
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  be violated. Even worse, $H$ can be delayed indefinitely by
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  threads with lower priorities. For this let $L$ be in the
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  possession of a lock for a resource that also $H$ needs. $H$ must
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  therefore wait for $L$ to exit the critical section and release this
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  lock. The problem is that $L$ might in turn be blocked by any
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  thread with priority $M$, and so $H$ sits there potentially waiting
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  indefinitely. Since $H$ is blocked by threads with lower
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  priorities, the problem is called Priority Inversion. It was first
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  described in \cite{Lampson80} in the context of the
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  Mesa programming language designed for concurrent programming.
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  If the problem of Priority Inversion is ignored, real-time systems
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  can become unpredictable and resulting bugs can be hard to diagnose.
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  The classic example where this happened is the software that
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  controlled the Mars Pathfinder mission in 1997 \cite{Reeves98}.
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  Once the spacecraft landed, the software shut down at irregular
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  intervals leading to loss of project time as normal operation of the
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  craft could only resume the next day (the mission and data already
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  collected were fortunately not lost, because of a clever system
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  design).  The reason for the shutdowns was that the scheduling
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  software fell victim of Priority Inversion: a low priority thread
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  locking a resource prevented a high priority thread from running in
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  time leading to a system reset. Once the problem was found, it was
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  rectified by enabling the \emph{Priority Inheritance Protocol} (PIP)
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  \cite{Sha90}\footnote{Sha et al.~call it the \emph{Basic Priority
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  Inheritance Protocol} \cite{Sha90} and others sometimes also call it
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  \emph{Priority Boosting}.} in the scheduling software.
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  The idea behind PIP is to let the thread $L$ temporarily inherit
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  the high priority from $H$ until $L$ leaves the critical section
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  unlocking the resource. This solves the problem of $H$ having to
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  wait indefinitely, because $L$ cannot be blocked by threads having
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  priority $M$. While a few other solutions exist for the Priority
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  Inversion problem, PIP is one that is widely deployed and
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  implemented. This includes VxWorks (a proprietary real-time OS used
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  in the Mars Pathfinder mission, in Boeing's 787 Dreamliner, Honda's
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  ASIMO robot, etc.), but also the POSIX 1003.1c Standard realised for
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  example in libraries for FreeBSD, Solaris and Linux.
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  One advantage of PIP is that increasing the priority of a thread
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  can be dynamically calculated by the scheduler. This is in contrast
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  to, for example, \emph{Priority Ceiling} \cite{Sha90}, another
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  solution to the Priority Inversion problem, which requires static
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  analysis of the program in order to prevent Priority
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  Inversion. However, there has also been strong criticism against
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  PIP. For instance, PIP cannot prevent deadlocks when lock
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  dependencies are circular, and also blocking times can be
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  substantial (more than just the duration of a critical section).
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  Though, most criticism against PIP centres around unreliable
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  implementations and PIP being too complicated and too inefficient.
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  For example, Yodaiken writes in \cite{Yodaiken02}:
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  \begin{quote}
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  \it{}``Priority inheritance is neither efficient nor reliable. Implementations
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  are either incomplete (and unreliable) or surprisingly complex and intrusive.''
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  \end{quote}
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  \noindent
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  He suggests to avoid PIP altogether by not allowing critical
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  sections to be preempted. Unfortunately, this solution does not
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  help in real-time systems with low latency \emph{requirements}.
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  In our opinion, there is clearly a need for investigating correct
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  algorithms for PIP. A few specifications for PIP exist (in English)
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  and also a few high-level descriptions of implementations (e.g.~in
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  the textbook \cite[Section 5.6.5]{Vahalia96}), but they help little
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  with actual implementations. That this is a problem in practise is
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  proved by an email from Baker, who wrote on 13 July 2009 on the Linux
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  Kernel mailing list:
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  \begin{quote}
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  \it{}``I observed in the kernel code (to my disgust), the Linux PIP
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  implementation is a nightmare: extremely heavy weight, involving
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  maintenance of a full wait-for graph, and requiring updates for a
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  range of events, including priority changes and interruptions of
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  wait operations.''
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  \end{quote}
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  \noindent
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  The criticism by Yodaiken, Baker and others suggests to us to look
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  again at PIP from a more abstract level (but still concrete enough
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  to inform an implementation), and makes PIP an ideal candidate for a
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  formal verification. One reason, of course, is that the original
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  presentation of PIP~\cite{Sha90}, despite being informally
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  ``proved'' correct, is actually \emph{flawed}. 
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  Yodaiken \cite{Yodaiken02} points to a subtlety that had been
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  overlooked in the informal proof by Sha et al. They specify in
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  \cite{Sha90} that after the thread (whose priority has been raised)
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  completes its critical section and releases the lock, it ``returns
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  to its original priority level.'' This leads them to believe that an
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  implementation of PIP is ``rather straightforward''~\cite{Sha90}.
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  Unfortunately, as Yodaiken points out, this behaviour is too
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  simplistic.  Consider the case where the low priority thread $L$
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  locks \emph{two} resources, and two high-priority threads $H$ and
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  $H'$ each wait for one of them.  If $L$ releases one resource
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  so that $H$, say, can proceed, then we still have Priority Inversion
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  with $H'$ (which waits for the other resource). The correct
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  behaviour for $L$ is to revert to the highest remaining priority of
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  the threads that it blocks. The advantage of formalising the
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  correctness of a high-level specification of PIP in a theorem prover
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  is that such issues clearly show up and cannot be overlooked as in
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  informal reasoning (since we have to analyse all possible behaviours
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  of threads, i.e.~\emph{traces}, that could possibly happen).\medskip
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  \noindent
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  {\bf Contributions:} There have been earlier formal investigations
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  into PIP \cite{conf/fase/JahierHR09,WellingsBSB07,Faria08}, but they
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  are using model checking technology. As far as we are aware, this is
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  the first formalised proof for the correctness of PIP. In contrast
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  to model checking, our formalisation provides insight into why PIP
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  is correct and allows us to prove stronger properties. For this Isar
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  and Isabelle/HOL is an attractive tool for exploring definitions and
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  keeping proofs consistent.
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  For example, we find through formalization that the choice of next 
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  thread to take a lock when a resource is released is irrelevant for 
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  the very basic property of PIP to hold.
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  Despite the wide use of Priority Inheritance Protocol in real time
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  operating system, it’s correctness has never been formally proved
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  and mechanically checked. All existing verification are based on
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  model checking technology. Full automatic verification gives little
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  help to understand why the protocol is correct. And results such
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  obtained only apply to models of limited size. This paper presents a
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  formal verification based on theorem proving. Machine checked formal
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  proof does help to get deeper understanding. We found the fact which
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  is not mentioned in the literature, that the choice of next thread
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  to take over when an critical resource is release does not affect
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  the correctness of the protocol. The paper also shows how formal
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  proof can help to construct correct and efficient implementation.
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  vt (valid trace) was introduced earlier, cite
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  Paulson's method has not been used outside security field, except
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  work by Zhang et al.
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  How did Sha et al prove it....they did not use Paulson's method.
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*}
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section {* Formal Model of the Priority Inheritance Protocol *}
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text {*
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  The Priority Inheritance Protocol, short PIP, is a scheduling
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  algorithm for a single-processor system.\footnote{We shall come back
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  later to the case of PIP on multi-processor systems.} Our model of
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  PIP is based on Paulson's inductive approach to protocol
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  verification \cite{Paulson98}, where the \emph{state} of a system is
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  given by a list of events that happened so far.  \emph{Events} of PIP fall
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  into five categories defined as the datatype:
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  \begin{isabelle}\ \ \ \ \ %%%
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  \mbox{\begin{tabular}{r@ {\hspace{2mm}}c@ {\hspace{2mm}}l@ {\hspace{7mm}}l}
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  \isacommand{datatype} event 
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  & @{text "="} & @{term "Create thread priority"}\\
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  & @{text "|"} & @{term "Exit thread"} \\
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  & @{text "|"} & @{term "Set thread priority"} & {\rm reset of the priority for} @{text thread}\\
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  & @{text "|"} & @{term "P thread cs"} & {\rm request of resource} @{text "cs"} {\rm by} @{text "thread"}\\
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  & @{text "|"} & @{term "V thread cs"} & {\rm release of resource} @{text "cs"} {\rm by} @{text "thread"}
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  \end{tabular}}
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  \end{isabelle}
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  \noindent
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  whereby threads, priorities and (critical) resources are represented
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  as natural numbers. The event @{term Set} models the situation that
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  a thread obtains a new priority given by the programmer or
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  user (for example via the {\tt nice} utility under UNIX).  As in Paulson's work, we
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  need to define functions that allow us to make some observations
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  about states.  One, called @{term threads}, calculates the set of
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  ``live'' threads that we have seen so far:
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  \begin{isabelle}\ \ \ \ \ %%%
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  \mbox{\begin{tabular}{lcl}
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  @{thm (lhs) threads.simps(1)} & @{text "\<equiv>"} & 
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    @{thm (rhs) threads.simps(1)}\\
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  @{thm (lhs) threads.simps(2)[where thread="th"]} & @{text "\<equiv>"} & 
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    @{thm (rhs) threads.simps(2)[where thread="th"]}\\
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  @{thm (lhs) threads.simps(3)[where thread="th"]} & @{text "\<equiv>"} & 
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    @{thm (rhs) threads.simps(3)[where thread="th"]}\\
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  @{term "threads (DUMMY#s)"} & @{text "\<equiv>"} & @{term "threads s"}\\
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  \end{tabular}}
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  \end{isabelle}
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  \noindent
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  In this definition @{term "DUMMY # DUMMY"} stands for list-cons.
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  Another function calculates the priority for a thread @{text "th"}, which is 
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  defined as
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  \begin{isabelle}\ \ \ \ \ %%%
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  \mbox{\begin{tabular}{lcl}
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  @{thm (lhs) original_priority.simps(1)[where thread="th"]} & @{text "\<equiv>"} & 
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    @{thm (rhs) original_priority.simps(1)[where thread="th"]}\\
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  @{thm (lhs) original_priority.simps(2)[where thread="th" and thread'="th'"]} & @{text "\<equiv>"} & 
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    @{thm (rhs) original_priority.simps(2)[where thread="th" and thread'="th'"]}\\
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  @{thm (lhs) original_priority.simps(3)[where thread="th" and thread'="th'"]} & @{text "\<equiv>"} & 
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    @{thm (rhs) original_priority.simps(3)[where thread="th" and thread'="th'"]}\\
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  @{term "original_priority th (DUMMY#s)"} & @{text "\<equiv>"} & @{term "original_priority th s"}\\
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  \end{tabular}}
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  \end{isabelle}
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  \noindent
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  In this definition we set @{text 0} as the default priority for
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  threads that have not (yet) been created. The last function we need 
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  calculates the ``time'', or index, at which time a process had its 
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  priority last set.
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  \begin{isabelle}\ \ \ \ \ %%%
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  \mbox{\begin{tabular}{lcl}
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  @{thm (lhs) birthtime.simps(1)[where thread="th"]} & @{text "\<equiv>"} & 
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    @{thm (rhs) birthtime.simps(1)[where thread="th"]}\\
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  @{thm (lhs) birthtime.simps(2)[where thread="th" and thread'="th'"]} & @{text "\<equiv>"} & 
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    @{thm (rhs) birthtime.simps(2)[where thread="th" and thread'="th'"]}\\
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  @{thm (lhs) birthtime.simps(3)[where thread="th" and thread'="th'"]} & @{text "\<equiv>"} & 
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    @{thm (rhs) birthtime.simps(3)[where thread="th" and thread'="th'"]}\\
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  @{term "birthtime th (DUMMY#s)"} & @{text "\<equiv>"} & @{term "birthtime th s"}\\
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  \end{tabular}}
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  \end{isabelle}
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  \noindent
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  In this definition @{term "length s"} stands for the length of the list
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  of events @{text s}. Again the default value in this function is @{text 0}
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  for threads that have not been created yet. A \emph{precedence} of a thread @{text th} in a 
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  state @{text s} is the pair of natural numbers defined as
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  \begin{isabelle}\ \ \ \ \ %%%
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  @{thm preced_def[where thread="th"]}
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  \end{isabelle}
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  \noindent
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  The point of precedences is to schedule threads not according to priorities (because what should
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  we do in case two threads have the same priority), but according to precedences. 
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  Precedences allow us to always discriminate between two threads with equal priority by 
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  taking into account the time when the priority was last set. We order precedences so 
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  that threads with the same priority get a higher precedence if their priority has been 
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  set earlier, since for such threads it is more urgent to finish their work. In an implementation
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  this choice would translate to a quite natural FIFO-scheduling of processes with 
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  the same priority.
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  Next, we introduce the concept of \emph{waiting queues}. They are
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  lists of threads associated with every resource. The first thread in
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  this list (i.e.~the head, or short @{term hd}) is chosen to be the one 
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  that is in possession of the
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  ``lock'' of the corresponding resource. We model waiting queues as
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  functions, below abbreviated as @{text wq}. They take a resource as
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  argument and return a list of threads.  This allows us to define
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  when a thread \emph{holds}, respectively \emph{waits} for, a
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  resource @{text cs} given a waiting queue function @{text wq}.
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  \begin{isabelle}\ \ \ \ \ %%%
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  \begin{tabular}{@ {}l}
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  @{thm cs_holding_def[where thread="th"]}\\
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  @{thm cs_waiting_def[where thread="th"]}
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  \end{tabular}
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  \end{isabelle}
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  \noindent
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  In this definition we assume @{text "set"} converts a list into a set.
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  At the beginning, that is in the state where no thread is created yet, 
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  the waiting queue function will be the function that returns the
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  empty list for every resource.
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  \begin{isabelle}\ \ \ \ \ %%%
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  @{abbrev all_unlocked}\hfill\numbered{allunlocked}
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  \end{isabelle}
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  \noindent
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  Using @{term "holding"} and @{term waiting}, we can introduce \emph{Resource Allocation Graphs} 
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  (RAG), which represent the dependencies between threads and resources.
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  We represent RAGs as relations using pairs of the form
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  \begin{isabelle}\ \ \ \ \ %%%
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  @{term "(Th th, Cs cs)"} \hspace{5mm}{\rm and}\hspace{5mm}
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  @{term "(Cs cs, Th th)"}
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  \end{isabelle}
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  \noindent
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  where the first stands for a \emph{waiting edge} and the second for a 
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  \emph{holding edge} (@{term Cs} and @{term Th} are constructors of a 
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  datatype for vertices). Given a waiting queue function, a RAG is defined 
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  as
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  \begin{isabelle}\ \ \ \ \ %%%
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  @{thm cs_depend_def}
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  \end{isabelle}
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  \noindent
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  Given three threads and three resources, an instance of a RAG is as follows:
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  \begin{center}
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  \newcommand{\fnt}{\fontsize{7}{8}\selectfont}
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  \begin{tikzpicture}[scale=1]
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  %%\draw[step=2mm] (-3,2) grid (1,-1);
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  \node (A) at (0,0) [draw, rounded corners=1mm, rectangle, very thick] {@{text "th\<^isub>0"}};
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  \node (B) at (2,0) [draw, circle, very thick, inner sep=0.4mm] {@{text "cs\<^isub>1"}};
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  \node (C) at (4,0.7) [draw, rounded corners=1mm, rectangle, very thick] {@{text "th\<^isub>1"}};
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  \node (D) at (4,-0.7) [draw, rounded corners=1mm, rectangle, very thick] {@{text "th\<^isub>2"}};
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  \node (E) at (6,-0.7) [draw, circle, very thick, inner sep=0.4mm] {@{text "cs\<^isub>2"}};
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  \node (E1) at (6, 0.2) [draw, circle, very thick, inner sep=0.4mm] {@{text "cs\<^isub>3"}};
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  \node (F) at (8,-0.7) [draw, rounded corners=1mm, rectangle, very thick] {@{text "th\<^isub>3"}};
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  \draw [<-,line width=0.6mm] (A) to node [pos=0.54,sloped,above=-0.5mm] {\fnt{}holding}  (B);
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  \draw [->,line width=0.6mm] (C) to node [pos=0.4,sloped,above=-0.5mm] {\fnt{}waiting}  (B);
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  \draw [->,line width=0.6mm] (D) to node [pos=0.4,sloped,below=-0.5mm] {\fnt{}waiting}  (B);
300
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  \draw [<-,line width=0.6mm] (D) to node [pos=0.54,sloped,below=-0.5mm] {\fnt{}holding}  (E);
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  \draw [<-,line width=0.6mm] (D) to node [pos=0.54,sloped,above=-0.5mm] {\fnt{}holding}  (E1);
298
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  \draw [->,line width=0.6mm] (F) to node [pos=0.45,sloped,below=-0.5mm] {\fnt{}waiting}  (E);
291
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  \end{tikzpicture}
290
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   355
  \end{center}
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   356
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   357
  \noindent
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   358
  The use of relations for representing RAGs allows us to conveniently define
290
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   359
  the notion of the \emph{dependants} of a thread. This is defined as
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   360
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   361
  \begin{isabelle}\ \ \ \ \ %%%
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   362
  @{thm cs_dependents_def}
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   363
  \end{isabelle}
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   364
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  \noindent
296
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   366
  This definition needs to account for all threads that wait for a thread to
290
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   367
  release a resource. This means we need to include threads that transitively
298
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   368
  wait for a resource being released (in the picture above this means the dependants
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   369
  of @{text "th\<^isub>0"} are @{text "th\<^isub>1"} and @{text "th\<^isub>2"}, but also @{text "th\<^isub>3"}, 
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   370
  which cannot make any progress unless @{text "th\<^isub>2"} makes progress, which
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   371
  in turn needs to wait for @{text "th\<^isub>1"} to finish). If there is a circle in a RAG, then clearly
291
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   372
  we have a deadlock. Therefore when a thread requests a resource,
298
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  we must ensure that the resulting RAG is not circular. 
291
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   374
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   375
  Next we introduce the notion of the \emph{current precedence} of a thread @{text th} in a 
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  state @{text s}. It is defined as
291
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   377
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   378
  \begin{isabelle}\ \ \ \ \ %%%
299
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   379
  @{thm cpreced_def2}\hfill\numbered{cpreced}
291
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   380
  \end{isabelle}
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   381
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   382
  \noindent
293
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   383
  While the precedence @{term prec} of a thread is determined by the programmer 
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   384
  (for example when the thread is
291
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diff changeset
   385
  created), the point of the current precedence is to let scheduler increase this
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diff changeset
   386
  priority, if needed according to PIP. Therefore the current precedence of @{text th} is
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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   387
  given as the maximum of the precedence @{text th} has in state @{text s} \emph{and} all 
296
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   388
  processes that are dependants of @{text th}. Since the notion @{term "dependants"} is
291
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diff changeset
   389
  defined as the transitive closure of all dependent threads, we deal correctly with the 
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   390
  problem in the algorithm by Sha et al.~\cite{Sha90} where a priority of a thread is
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   391
  lowered prematurely.
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   392
  
298
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   393
  The next function, called @{term schs}, defines the behaviour of the scheduler. It will be defined
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diff changeset
   394
  by recursion on the state (a list of events); @{term "schs"} returns a \emph{schedule state}, which 
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   395
  we represent as a record consisting of two
296
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   396
  functions:
293
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diff changeset
   397
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   398
  \begin{isabelle}\ \ \ \ \ %%%
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   399
  @{text "\<lparr>wq_fun, cprec_fun\<rparr>"}
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   400
  \end{isabelle}
291
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diff changeset
   401
294
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   402
  \noindent
299
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   403
  The first function is a waiting queue function (that is it takes a resource @{text "cs"} and returns the
296
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diff changeset
   404
  corresponding list of threads that wait for it), the second is a function that takes
299
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diff changeset
   405
  a thread and returns its current precedence (see \eqref{cpreced}). We assume the usual getter and 
296
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diff changeset
   406
  setter methods for such records.
294
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diff changeset
   407
301
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diff changeset
   408
  In the initial state, the scheduler starts with all resources unlocked (see \eqref{allunlocked}) and the
298
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diff changeset
   409
  current precedence of every thread is initialised with @{term "Prc 0 0"}; that means 
299
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diff changeset
   410
  \mbox{@{abbrev initial_cprec}}. Therefore
296
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diff changeset
   411
  we have
291
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diff changeset
   412
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   413
  \begin{isabelle}\ \ \ \ \ %%%
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   414
  \begin{tabular}{@ {}l}
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   415
  @{thm (lhs) schs.simps(1)} @{text "\<equiv>"}\\ 
294
bc5bf9e9ada2 renamed waiting_queue -> wq_fun; cur_preced -> cprec_fun
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diff changeset
   416
  \hspace{5mm}@{term "(|wq_fun = all_unlocked, cprec_fun = (\<lambda>_::thread. Prc 0 0)|)"}
291
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   417
  \end{tabular}
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   418
  \end{isabelle}
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   419
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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   420
  \noindent
296
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   421
  The cases for @{term Create}, @{term Exit} and @{term Set} are also straightforward:
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diff changeset
   422
  we calculate the waiting queue function of the (previous) state @{text s}; 
298
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diff changeset
   423
  this waiting queue function @{text wq} is unchanged in the next schedule state---because
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diff changeset
   424
  none of these events lock or release any resources; 
296
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diff changeset
   425
  for calculating the next @{term "cprec_fun"}, we use @{text wq} and the function 
298
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diff changeset
   426
  @{term cpreced}. This gives the following three clauses for @{term schs}:
290
6a6d0bd16035 more on paper
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diff changeset
   427
6a6d0bd16035 more on paper
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diff changeset
   428
  \begin{isabelle}\ \ \ \ \ %%%
291
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diff changeset
   429
  \begin{tabular}{@ {}l}
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   430
  @{thm (lhs) schs.simps(2)} @{text "\<equiv>"}\\ 
294
bc5bf9e9ada2 renamed waiting_queue -> wq_fun; cur_preced -> cprec_fun
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diff changeset
   431
  \hspace{5mm}@{text "let"} @{text "wq = wq_fun (schs s)"} @{text "in"}\\
298
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   432
  \hspace{8mm}@{term "(|wq_fun = wq\<iota>, cprec_fun = cpreced wq\<iota> (Create th prio # s)|)"}\smallskip\\
291
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   433
  @{thm (lhs) schs.simps(3)} @{text "\<equiv>"}\\
294
bc5bf9e9ada2 renamed waiting_queue -> wq_fun; cur_preced -> cprec_fun
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diff changeset
   434
  \hspace{5mm}@{text "let"} @{text "wq = wq_fun (schs s)"} @{text "in"}\\
bc5bf9e9ada2 renamed waiting_queue -> wq_fun; cur_preced -> cprec_fun
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diff changeset
   435
  \hspace{8mm}@{term "(|wq_fun = wq\<iota>, cprec_fun = cpreced wq\<iota> (Exit th # s)|)"}\smallskip\\
291
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   436
  @{thm (lhs) schs.simps(4)} @{text "\<equiv>"}\\ 
294
bc5bf9e9ada2 renamed waiting_queue -> wq_fun; cur_preced -> cprec_fun
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diff changeset
   437
  \hspace{5mm}@{text "let"} @{text "wq = wq_fun (schs s)"} @{text "in"}\\
bc5bf9e9ada2 renamed waiting_queue -> wq_fun; cur_preced -> cprec_fun
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diff changeset
   438
  \hspace{8mm}@{term "(|wq_fun = wq\<iota>, cprec_fun = cpreced wq\<iota> (Set th prio # s)|)"}
291
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   439
  \end{tabular}
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   440
  \end{isabelle}
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   441
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   442
  \noindent 
300
8524f94d251b correct RAG
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diff changeset
   443
  More interesting are the cases when a resource, say @{text cs}, is locked or released. In these cases
8524f94d251b correct RAG
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diff changeset
   444
  we need to calculate a new waiting queue function. For the event @{term "P th cs"}, we have to update
296
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diff changeset
   445
  the function so that the new thread list for @{text cs} is old thread list plus the thread @{text th} 
300
8524f94d251b correct RAG
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diff changeset
   446
  appended to the end of that list (remember the head of this list is seen to be in the possession of this
291
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   447
  resource).
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   448
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   449
  \begin{isabelle}\ \ \ \ \ %%%
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   450
  \begin{tabular}{@ {}l}
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   451
  @{thm (lhs) schs.simps(5)} @{text "\<equiv>"}\\ 
294
bc5bf9e9ada2 renamed waiting_queue -> wq_fun; cur_preced -> cprec_fun
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diff changeset
   452
  \hspace{5mm}@{text "let"} @{text "wq = wq_fun (schs s)"} @{text "in"}\\
291
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   453
  \hspace{5mm}@{text "let"} @{text "new_wq = wq(cs := (wq cs @ [th]))"} @{text "in"}\\
294
bc5bf9e9ada2 renamed waiting_queue -> wq_fun; cur_preced -> cprec_fun
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diff changeset
   454
  \hspace{8mm}@{term "(|wq_fun = new_wq, cprec_fun = cpreced new_wq (P th cs # s)|)"}
291
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   455
  \end{tabular}
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   456
  \end{isabelle}
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   457
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   458
  \noindent
300
8524f94d251b correct RAG
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diff changeset
   459
  The clause for event @{term "V th cs"} is similar, except that we need to update the waiting queue function
301
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parents: 300
diff changeset
   460
  so that the thread that possessed the lock is deleted from the corresponding thread list. For this 
urbanc
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diff changeset
   461
  list transformation, we use
296
2c8dcf010567 spell check; release
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diff changeset
   462
  the auxiliary function @{term release}. A simple version of @{term release} would
298
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   463
  just delete this thread and return the rest, namely
291
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   464
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   465
  \begin{isabelle}\ \ \ \ \ %%%
296
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diff changeset
   466
  \begin{tabular}{@ {}lcl}
2c8dcf010567 spell check; release
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diff changeset
   467
  @{term "release []"} & @{text "\<equiv>"} & @{term "[]"}\\
2c8dcf010567 spell check; release
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diff changeset
   468
  @{term "release (DUMMY # qs)"} & @{text "\<equiv>"} & @{term "qs"}\\
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diff changeset
   469
  \end{tabular}
291
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   470
  \end{isabelle}
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   471
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   472
  \noindent
300
8524f94d251b correct RAG
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diff changeset
   473
  In practice, however, often the thread with the highest precedence in the list will get the
296
2c8dcf010567 spell check; release
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diff changeset
   474
  lock next. We have implemented this choice, but later found out that the choice 
300
8524f94d251b correct RAG
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diff changeset
   475
  of which thread is chosen next is actually irrelevant for the correctness of PIP.
296
2c8dcf010567 spell check; release
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diff changeset
   476
  Therefore we prove the stronger result where @{term release} is defined as
2c8dcf010567 spell check; release
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parents: 294
diff changeset
   477
2c8dcf010567 spell check; release
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parents: 294
diff changeset
   478
  \begin{isabelle}\ \ \ \ \ %%%
2c8dcf010567 spell check; release
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diff changeset
   479
  \begin{tabular}{@ {}lcl}
2c8dcf010567 spell check; release
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diff changeset
   480
  @{term "release []"} & @{text "\<equiv>"} & @{term "[]"}\\
2c8dcf010567 spell check; release
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diff changeset
   481
  @{term "release (DUMMY # qs)"} & @{text "\<equiv>"} & @{term "SOME qs'. distinct qs' \<and> set qs' = set qs"}\\
2c8dcf010567 spell check; release
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diff changeset
   482
  \end{tabular}
2c8dcf010567 spell check; release
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diff changeset
   483
  \end{isabelle}
2c8dcf010567 spell check; release
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diff changeset
   484
2c8dcf010567 spell check; release
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diff changeset
   485
  \noindent
2c8dcf010567 spell check; release
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diff changeset
   486
  @{text "SOME"} stands for Hilbert's epsilon and implements an arbitrary
298
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   487
  choice for the next waiting list. It just has to be a list of distinctive threads and
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   488
  contain the same elements as @{text "qs"}. This gives for @{term V} the clause:
291
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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parents: 290
diff changeset
   489
 
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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parents: 290
diff changeset
   490
  \begin{isabelle}\ \ \ \ \ %%%
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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parents: 290
diff changeset
   491
  \begin{tabular}{@ {}l}
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   492
  @{thm (lhs) schs.simps(6)} @{text "\<equiv>"}\\
294
bc5bf9e9ada2 renamed waiting_queue -> wq_fun; cur_preced -> cprec_fun
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diff changeset
   493
  \hspace{5mm}@{text "let"} @{text "wq = wq_fun (schs s)"} @{text "in"}\\
291
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   494
  \hspace{5mm}@{text "let"} @{text "new_wq = release (wq cs)"} @{text "in"}\\
294
bc5bf9e9ada2 renamed waiting_queue -> wq_fun; cur_preced -> cprec_fun
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diff changeset
   495
  \hspace{8mm}@{term "(|wq_fun = new_wq, cprec_fun = cpreced new_wq (V th cs # s)|)"}
291
5ef9f6ebe827 more on paper; modified schs functions; it is still compatible with the old definition
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diff changeset
   496
  \end{tabular}
290
6a6d0bd16035 more on paper
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diff changeset
   497
  \end{isabelle}
6a6d0bd16035 more on paper
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diff changeset
   498
300
8524f94d251b correct RAG
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diff changeset
   499
  Having the scheduler function @{term schs} at our disposal, we can ``lift'', or
8524f94d251b correct RAG
urbanc
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diff changeset
   500
  overload, the notions
8524f94d251b correct RAG
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diff changeset
   501
  @{term waiting}, @{term holding}, @{term depend} and @{term cp} to operate on states only.
286
572f202659ff corrections by Xingyuan
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diff changeset
   502
572f202659ff corrections by Xingyuan
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parents: 285
diff changeset
   503
  \begin{isabelle}\ \ \ \ \ %%%
298
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diff changeset
   504
  \begin{tabular}{@ {}rcl}
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diff changeset
   505
  @{thm (lhs) s_holding_abv} & @{text "\<equiv>"} & @{thm (rhs) s_holding_abv}\\
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   506
  @{thm (lhs) s_waiting_abv} & @{text "\<equiv>"} & @{thm (rhs) s_waiting_abv}\\
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   507
  @{thm (lhs) s_depend_abv}  & @{text "\<equiv>"} & @{thm (rhs) s_depend_abv}\\
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   508
  @{thm (lhs) cp_def}        & @{text "\<equiv>"} & @{thm (rhs) cp_def}
287
440382eb6427 more on the specification section
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diff changeset
   509
  \end{tabular}
440382eb6427 more on the specification section
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parents: 286
diff changeset
   510
  \end{isabelle}
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diff changeset
   511
298
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diff changeset
   512
  \noindent
300
8524f94d251b correct RAG
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diff changeset
   513
  With these abbreviations we can introduce 
8524f94d251b correct RAG
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diff changeset
   514
  the notion of threads being @{term readys} in a state (i.e.~threads
298
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diff changeset
   515
  that do not wait for any resource) and the running thread.
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diff changeset
   516
287
440382eb6427 more on the specification section
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diff changeset
   517
  \begin{isabelle}\ \ \ \ \ %%%
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diff changeset
   518
  \begin{tabular}{@ {}l}
440382eb6427 more on the specification section
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diff changeset
   519
  @{thm readys_def}\\
440382eb6427 more on the specification section
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diff changeset
   520
  @{thm runing_def}\\
286
572f202659ff corrections by Xingyuan
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diff changeset
   521
  \end{tabular}
572f202659ff corrections by Xingyuan
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diff changeset
   522
  \end{isabelle}
284
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diff changeset
   523
298
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diff changeset
   524
  \noindent
299
4fcd802eba59 small polishing
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diff changeset
   525
  In this definition @{term "f ` S"} stands for the set @{text S} under the image of the 
4fcd802eba59 small polishing
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diff changeset
   526
  function @{text f}. 
298
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   527
  Note that in the initial case, that is where the list of events is empty, the set 
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diff changeset
   528
  @{term threads} is empty and therefore there is no thread ready nor a running.
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   529
  If there is one or more threads ready, then there can only be \emph{one} thread
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   530
  running, namely the one whose current precedence is equal to the maximum of all ready 
300
8524f94d251b correct RAG
urbanc
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diff changeset
   531
  threads. We use the set-comprehension to capture both possibilites.
8524f94d251b correct RAG
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diff changeset
   532
  We can now also define the set of resources that are locked by a thread in any
298
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   533
  given state.
284
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diff changeset
   534
298
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diff changeset
   535
  \begin{isabelle}\ \ \ \ \ %%%
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   536
  @{thm holdents_def}
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diff changeset
   537
  \end{isabelle}
284
d296cb127fcb more on paper
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diff changeset
   538
298
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   539
  \noindent
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   540
  These resources are given by the holding edges in the RAG.
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   541
299
4fcd802eba59 small polishing
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diff changeset
   542
  Finally we can define what a \emph{valid state} is in our PIP. For example we cannot exptect to
298
f2e0d031a395 completed model section; vt has only state as argument
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parents: 297
diff changeset
   543
  be able to exit a thread, if it was not created yet. These validity constraints
299
4fcd802eba59 small polishing
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diff changeset
   544
  are characterised by the inductive predicate @{term "step"}. We give five 
298
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   545
  inference rules relating a state and an event that can happen next.
284
d296cb127fcb more on paper
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diff changeset
   546
d296cb127fcb more on paper
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parents: 283
diff changeset
   547
  \begin{center}
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diff changeset
   548
  \begin{tabular}{c}
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diff changeset
   549
  @{thm[mode=Rule] thread_create[where thread=th]}\hspace{1cm}
298
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   550
  @{thm[mode=Rule] thread_exit[where thread=th]}
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   551
  \end{tabular}
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   552
  \end{center}
f2e0d031a395 completed model section; vt has only state as argument
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parents: 297
diff changeset
   553
f2e0d031a395 completed model section; vt has only state as argument
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parents: 297
diff changeset
   554
  \noindent
f2e0d031a395 completed model section; vt has only state as argument
urbanc
parents: 297
diff changeset
   555
  The first rule states that a thread can only be created, if it does not yet exists.
f2e0d031a395 completed model section; vt has only state as argument
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parents: 297
diff changeset
   556
  Similarly, the second rule states that a thread can only be terminated if it was
301
urbanc
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diff changeset
   557
  running and does not lock any resources anymore (to simplify ). The event @{text Set} can happen
298
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   558
  if the corresponding thread is running. 
284
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diff changeset
   559
298
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   560
  \begin{center}
f2e0d031a395 completed model section; vt has only state as argument
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parents: 297
diff changeset
   561
  @{thm[mode=Rule] thread_set[where thread=th]}
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   562
  \end{center}
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   563
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   564
  \noindent
301
urbanc
parents: 300
diff changeset
   565
  If a thread wants to lock a resource, then the thread needs to be
urbanc
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diff changeset
   566
  running and also we have to make sure that the resource lock does
urbanc
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diff changeset
   567
  not lead to a cycle in the RAG. In practice, ensuring the latter is
urbanc
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diff changeset
   568
  of course the responsibility of the programmer.  Here in our formal
urbanc
parents: 300
diff changeset
   569
  model we just exclude such problematic cases in order to make
urbanc
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diff changeset
   570
  some meaningful statements about PIP.\footnote{This situation is
urbanc
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diff changeset
   571
  similar to the infamous occurs check in Prolog: in order to say
urbanc
parents: 300
diff changeset
   572
  anything meaningful about unification, we need to perform an occurs
urbanc
parents: 300
diff changeset
   573
  check; but in practice the occurs check is ommited and the
urbanc
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diff changeset
   574
  responsibility to avoid problems rests with the programmer.}
urbanc
parents: 300
diff changeset
   575
  Similarly, if a thread wants to release a lock on a resource, then
urbanc
parents: 300
diff changeset
   576
  it must be running and in the possession of that lock. This is
urbanc
parents: 300
diff changeset
   577
  formally given by the last two inference rules of @{term step}.
298
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   578
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   579
  \begin{center}
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   580
  \begin{tabular}{c}
284
d296cb127fcb more on paper
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diff changeset
   581
  @{thm[mode=Rule] thread_P[where thread=th]}\medskip\\
d296cb127fcb more on paper
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diff changeset
   582
  @{thm[mode=Rule] thread_V[where thread=th]}\\
d296cb127fcb more on paper
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diff changeset
   583
  \end{tabular}
d296cb127fcb more on paper
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diff changeset
   584
  \end{center}
298
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   585
  
f2e0d031a395 completed model section; vt has only state as argument
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parents: 297
diff changeset
   586
  \noindent
f2e0d031a395 completed model section; vt has only state as argument
urbanc
parents: 297
diff changeset
   587
  A valid state of PIP can then be conveniently be defined as follows:
284
d296cb127fcb more on paper
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diff changeset
   588
d296cb127fcb more on paper
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parents: 283
diff changeset
   589
  \begin{center}
d296cb127fcb more on paper
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diff changeset
   590
  \begin{tabular}{c}
298
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   591
  @{thm[mode=Axiom] vt_nil}\hspace{1cm}
f2e0d031a395 completed model section; vt has only state as argument
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diff changeset
   592
  @{thm[mode=Rule] vt_cons}
284
d296cb127fcb more on paper
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diff changeset
   593
  \end{tabular}
d296cb127fcb more on paper
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parents: 283
diff changeset
   594
  \end{center}
d296cb127fcb more on paper
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diff changeset
   595
298
f2e0d031a395 completed model section; vt has only state as argument
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parents: 297
diff changeset
   596
  \noindent
f2e0d031a395 completed model section; vt has only state as argument
urbanc
parents: 297
diff changeset
   597
  This completes our formal model of PIP. In the next section we present
f2e0d031a395 completed model section; vt has only state as argument
urbanc
parents: 297
diff changeset
   598
  properties that show our version of PIP is correct.
f2e0d031a395 completed model section; vt has only state as argument
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parents: 297
diff changeset
   599
*}
274
83b0317370c2 more on intro
urbanc
parents: 273
diff changeset
   600
298
f2e0d031a395 completed model section; vt has only state as argument
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parents: 297
diff changeset
   601
section {* Correctness Proof *}
f2e0d031a395 completed model section; vt has only state as argument
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parents: 297
diff changeset
   602
301
urbanc
parents: 300
diff changeset
   603
urbanc
parents: 300
diff changeset
   604
(*<*)
urbanc
parents: 300
diff changeset
   605
context extend_highest_gen
urbanc
parents: 300
diff changeset
   606
begin
urbanc
parents: 300
diff changeset
   607
(*>*)
urbanc
parents: 300
diff changeset
   608
urbanc
parents: 300
diff changeset
   609
print_locale extend_highest_gen
urbanc
parents: 300
diff changeset
   610
thm extend_highest_gen_def
urbanc
parents: 300
diff changeset
   611
thm extend_highest_gen_axioms_def
urbanc
parents: 300
diff changeset
   612
thm highest_gen_def
urbanc
parents: 300
diff changeset
   613
text {* 
urbanc
parents: 300
diff changeset
   614
  Main lemma
urbanc
parents: 300
diff changeset
   615
urbanc
parents: 300
diff changeset
   616
  \begin{enumerate}
urbanc
parents: 300
diff changeset
   617
  \item @{term "s"} is a valid state (@{text "vt_s"}):
urbanc
parents: 300
diff changeset
   618
    @{thm  vt_s}.
urbanc
parents: 300
diff changeset
   619
  \item @{term "th"} is a living thread in @{term "s"} (@{text "threads_s"}):
urbanc
parents: 300
diff changeset
   620
    @{thm threads_s}.
urbanc
parents: 300
diff changeset
   621
  \item @{term "th"} has the highest precedence in @{term "s"} (@{text "highest"}):
urbanc
parents: 300
diff changeset
   622
    @{thm highest}.
urbanc
parents: 300
diff changeset
   623
  \item The precedence of @{term "th"} is @{term "Prc prio tm"} (@{text "preced_th"}):
urbanc
parents: 300
diff changeset
   624
    @{thm preced_th}.
urbanc
parents: 300
diff changeset
   625
  \end{enumerate}
urbanc
parents: 300
diff changeset
   626
urbanc
parents: 300
diff changeset
   627
urbanc
parents: 300
diff changeset
   628
  \begin{lemma}
urbanc
parents: 300
diff changeset
   629
  @{thm[mode=IfThen] moment_blocked}
urbanc
parents: 300
diff changeset
   630
  \end{lemma}
urbanc
parents: 300
diff changeset
   631
urbanc
parents: 300
diff changeset
   632
  \begin{theorem}
urbanc
parents: 300
diff changeset
   633
  @{thm[mode=IfThen] runing_inversion_2}
urbanc
parents: 300
diff changeset
   634
  \end{theorem}
urbanc
parents: 300
diff changeset
   635
urbanc
parents: 300
diff changeset
   636
  
urbanc
parents: 300
diff changeset
   637
urbanc
parents: 300
diff changeset
   638
urbanc
parents: 300
diff changeset
   639
TO DO 
urbanc
parents: 300
diff changeset
   640
urbanc
parents: 300
diff changeset
   641
*}
urbanc
parents: 300
diff changeset
   642
urbanc
parents: 300
diff changeset
   643
(*<*)
urbanc
parents: 300
diff changeset
   644
end
urbanc
parents: 300
diff changeset
   645
(*>*)
298
f2e0d031a395 completed model section; vt has only state as argument
urbanc
parents: 297
diff changeset
   646
f2e0d031a395 completed model section; vt has only state as argument
urbanc
parents: 297
diff changeset
   647
section {* Properties for an Implementation *}
f2e0d031a395 completed model section; vt has only state as argument
urbanc
parents: 297
diff changeset
   648
f2e0d031a395 completed model section; vt has only state as argument
urbanc
parents: 297
diff changeset
   649
text {* TO DO *}
f2e0d031a395 completed model section; vt has only state as argument
urbanc
parents: 297
diff changeset
   650
f2e0d031a395 completed model section; vt has only state as argument
urbanc
parents: 297
diff changeset
   651
section {* Conclusion *}
f2e0d031a395 completed model section; vt has only state as argument
urbanc
parents: 297
diff changeset
   652
300
8524f94d251b correct RAG
urbanc
parents: 299
diff changeset
   653
text {* 
8524f94d251b correct RAG
urbanc
parents: 299
diff changeset
   654
  The Priority Inheritance Protocol is a classic textbook algorithm
8524f94d251b correct RAG
urbanc
parents: 299
diff changeset
   655
  used in real-time systems in order to avoid the problem of Priority
8524f94d251b correct RAG
urbanc
parents: 299
diff changeset
   656
  Inversion.
8524f94d251b correct RAG
urbanc
parents: 299
diff changeset
   657
301
urbanc
parents: 300
diff changeset
   658
  A clear and simple understanding of the problem at hand is both a
urbanc
parents: 300
diff changeset
   659
  prerequisite and a byproduct of such an effort, because everything
urbanc
parents: 300
diff changeset
   660
  has finally be reduced to the very first principle to be checked
urbanc
parents: 300
diff changeset
   661
  mechanically.
urbanc
parents: 300
diff changeset
   662
300
8524f94d251b correct RAG
urbanc
parents: 299
diff changeset
   663
  TO DO 
8524f94d251b correct RAG
urbanc
parents: 299
diff changeset
   664
301
urbanc
parents: 300
diff changeset
   665
  no clue about multi-processor case according to \cite{Steinberg10} 
urbanc
parents: 300
diff changeset
   666
300
8524f94d251b correct RAG
urbanc
parents: 299
diff changeset
   667
*}
273
039711ba6cf9 slightly more on text
urbanc
parents: 272
diff changeset
   668
280
c91c2dd08599 updated
urbanc
parents: 279
diff changeset
   669
text {*
c91c2dd08599 updated
urbanc
parents: 279
diff changeset
   670
  \bigskip
284
d296cb127fcb more on paper
urbanc
parents: 283
diff changeset
   671
  The priority inversion phenomenon was first published in
d296cb127fcb more on paper
urbanc
parents: 283
diff changeset
   672
  \cite{Lampson80}.  The two protocols widely used to eliminate
d296cb127fcb more on paper
urbanc
parents: 283
diff changeset
   673
  priority inversion, namely PI (Priority Inheritance) and PCE
d296cb127fcb more on paper
urbanc
parents: 283
diff changeset
   674
  (Priority Ceiling Emulation), were proposed in \cite{Sha90}. PCE is
d296cb127fcb more on paper
urbanc
parents: 283
diff changeset
   675
  less convenient to use because it requires static analysis of
d296cb127fcb more on paper
urbanc
parents: 283
diff changeset
   676
  programs. Therefore, PI is more commonly used in
d296cb127fcb more on paper
urbanc
parents: 283
diff changeset
   677
  practice\cite{locke-july02}. However, as pointed out in the
d296cb127fcb more on paper
urbanc
parents: 283
diff changeset
   678
  literature, the analysis of priority inheritance protocol is quite
d296cb127fcb more on paper
urbanc
parents: 283
diff changeset
   679
  subtle\cite{yodaiken-july02}.  A formal analysis will certainly be
d296cb127fcb more on paper
urbanc
parents: 283
diff changeset
   680
  helpful for us to understand and correctly implement PI. All
d296cb127fcb more on paper
urbanc
parents: 283
diff changeset
   681
  existing formal analysis of PI
d296cb127fcb more on paper
urbanc
parents: 283
diff changeset
   682
  \cite{conf/fase/JahierHR09,WellingsBSB07,Faria08} are based on the
d296cb127fcb more on paper
urbanc
parents: 283
diff changeset
   683
  model checking technology. Because of the state explosion problem,
d296cb127fcb more on paper
urbanc
parents: 283
diff changeset
   684
  model check is much like an exhaustive testing of finite models with
d296cb127fcb more on paper
urbanc
parents: 283
diff changeset
   685
  limited size.  The results obtained can not be safely generalized to
d296cb127fcb more on paper
urbanc
parents: 283
diff changeset
   686
  models with arbitrarily large size. Worse still, since model
d296cb127fcb more on paper
urbanc
parents: 283
diff changeset
   687
  checking is fully automatic, it give little insight on why the
d296cb127fcb more on paper
urbanc
parents: 283
diff changeset
   688
  formal model is correct. It is therefore definitely desirable to
d296cb127fcb more on paper
urbanc
parents: 283
diff changeset
   689
  analyze PI using theorem proving, which gives more general results
d296cb127fcb more on paper
urbanc
parents: 283
diff changeset
   690
  as well as deeper insight. And this is the purpose of this paper
d296cb127fcb more on paper
urbanc
parents: 283
diff changeset
   691
  which gives a formal analysis of PI in the interactive theorem
d296cb127fcb more on paper
urbanc
parents: 283
diff changeset
   692
  prover Isabelle using Higher Order Logic (HOL). The formalization
262
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   693
  focuses on on two issues:
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   694
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   695
  \begin{enumerate}
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   696
  \item The correctness of the protocol model itself. A series of desirable properties is 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   697
    derived until we are fully convinced that the formal model of PI does 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   698
    eliminate priority inversion. And a better understanding of PI is so obtained 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   699
    in due course. For example, we find through formalization that the choice of 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   700
    next thread to take hold when a 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   701
    resource is released is irrelevant for the very basic property of PI to hold. 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   702
    A point never mentioned in literature. 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   703
  \item The correctness of the implementation. A series of properties is derived the meaning 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   704
    of which can be used as guidelines on how PI can be implemented efficiently and correctly. 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   705
  \end{enumerate} 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   706
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   707
  The rest of the paper is organized as follows: Section \ref{overview} gives an overview 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   708
  of PI. Section \ref{model} introduces the formal model of PI. Section \ref{general} 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   709
  discusses a series of basic properties of PI. Section \ref{extension} shows formally 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   710
  how priority inversion is controlled by PI. Section \ref{implement} gives properties 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   711
  which can be used for guidelines of implementation. Section \ref{related} discusses 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   712
  related works. Section \ref{conclusion} concludes the whole paper.
265
993068ce745f changed abstract, intro and IsaMakefile
urbanc
parents: 264
diff changeset
   713
273
039711ba6cf9 slightly more on text
urbanc
parents: 272
diff changeset
   714
  The basic priority inheritance protocol has two problems:
039711ba6cf9 slightly more on text
urbanc
parents: 272
diff changeset
   715
039711ba6cf9 slightly more on text
urbanc
parents: 272
diff changeset
   716
  It does not prevent a deadlock from happening in a program with circular lock dependencies.
039711ba6cf9 slightly more on text
urbanc
parents: 272
diff changeset
   717
  
039711ba6cf9 slightly more on text
urbanc
parents: 272
diff changeset
   718
  A chain of blocking may be formed; blocking duration can be substantial, though bounded.
039711ba6cf9 slightly more on text
urbanc
parents: 272
diff changeset
   719
265
993068ce745f changed abstract, intro and IsaMakefile
urbanc
parents: 264
diff changeset
   720
993068ce745f changed abstract, intro and IsaMakefile
urbanc
parents: 264
diff changeset
   721
  Contributions
993068ce745f changed abstract, intro and IsaMakefile
urbanc
parents: 264
diff changeset
   722
993068ce745f changed abstract, intro and IsaMakefile
urbanc
parents: 264
diff changeset
   723
  Despite the wide use of Priority Inheritance Protocol in real time operating
993068ce745f changed abstract, intro and IsaMakefile
urbanc
parents: 264
diff changeset
   724
  system, it's correctness has never been formally proved and mechanically checked. 
993068ce745f changed abstract, intro and IsaMakefile
urbanc
parents: 264
diff changeset
   725
  All existing verification are based on model checking technology. Full automatic
993068ce745f changed abstract, intro and IsaMakefile
urbanc
parents: 264
diff changeset
   726
  verification gives little help to understand why the protocol is correct. 
993068ce745f changed abstract, intro and IsaMakefile
urbanc
parents: 264
diff changeset
   727
  And results such obtained only apply to models of limited size. 
993068ce745f changed abstract, intro and IsaMakefile
urbanc
parents: 264
diff changeset
   728
  This paper presents a formal verification based on theorem proving. 
993068ce745f changed abstract, intro and IsaMakefile
urbanc
parents: 264
diff changeset
   729
  Machine checked formal proof does help to get deeper understanding. We found 
993068ce745f changed abstract, intro and IsaMakefile
urbanc
parents: 264
diff changeset
   730
  the fact which is not mentioned in the literature, that the choice of next 
993068ce745f changed abstract, intro and IsaMakefile
urbanc
parents: 264
diff changeset
   731
  thread to take over when an critical resource is release does not affect the correctness
993068ce745f changed abstract, intro and IsaMakefile
urbanc
parents: 264
diff changeset
   732
  of the protocol. The paper also shows how formal proof can help to construct 
993068ce745f changed abstract, intro and IsaMakefile
urbanc
parents: 264
diff changeset
   733
  correct and efficient implementation.\bigskip 
993068ce745f changed abstract, intro and IsaMakefile
urbanc
parents: 264
diff changeset
   734
262
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   735
*}
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   736
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   737
section {* An overview of priority inversion and priority inheritance \label{overview} *}
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   738
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   739
text {*
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   740
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   741
  Priority inversion refers to the phenomenon when a thread with high priority is blocked 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   742
  by a thread with low priority. Priority happens when the high priority thread requests 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   743
  for some critical resource already taken by the low priority thread. Since the high 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   744
  priority thread has to wait for the low priority thread to complete, it is said to be 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   745
  blocked by the low priority thread. Priority inversion might prevent high priority 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   746
  thread from fulfill its task in time if the duration of priority inversion is indefinite 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   747
  and unpredictable. Indefinite priority inversion happens when indefinite number 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   748
  of threads with medium priorities is activated during the period when the high 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   749
  priority thread is blocked by the low priority thread. Although these medium 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   750
  priority threads can not preempt the high priority thread directly, they are able 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   751
  to preempt the low priority threads and cause it to stay in critical section for 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   752
  an indefinite long duration. In this way, the high priority thread may be blocked indefinitely. 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   753
  
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   754
  Priority inheritance is one protocol proposed to avoid indefinite priority inversion. 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   755
  The basic idea is to let the high priority thread donate its priority to the low priority 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   756
  thread holding the critical resource, so that it will not be preempted by medium priority 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   757
  threads. The thread with highest priority will not be blocked unless it is requesting 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   758
  some critical resource already taken by other threads. Viewed from a different angle, 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   759
  any thread which is able to block the highest priority threads must already hold some 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   760
  critical resource. Further more, it must have hold some critical resource at the 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   761
  moment the highest priority is created, otherwise, it may never get change to run and 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   762
  get hold. Since the number of such resource holding lower priority threads is finite, 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   763
  if every one of them finishes with its own critical section in a definite duration, 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   764
  the duration the highest priority thread is blocked is definite as well. The key to 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   765
  guarantee lower priority threads to finish in definite is to donate them the highest 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   766
  priority. In such cases, the lower priority threads is said to have inherited the 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   767
  highest priority. And this explains the name of the protocol: 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   768
  {\em Priority Inheritance} and how Priority Inheritance prevents indefinite delay.
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   769
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   770
  The objectives of this paper are:
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   771
  \begin{enumerate}
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   772
  \item Build the above mentioned idea into formal model and prove a series of properties 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   773
    until we are convinced that the formal model does fulfill the original idea. 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   774
  \item Show how formally derived properties can be used as guidelines for correct 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   775
    and efficient implementation.
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   776
  \end{enumerate}
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   777
  The proof is totally formal in the sense that every detail is reduced to the 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   778
  very first principles of Higher Order Logic. The nature of interactive theorem 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   779
  proving is for the human user to persuade computer program to accept its arguments. 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   780
  A clear and simple understanding of the problem at hand is both a prerequisite and a 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   781
  byproduct of such an effort, because everything has finally be reduced to the very 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   782
  first principle to be checked mechanically. The former intuitive explanation of 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   783
  Priority Inheritance is just such a byproduct. 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   784
  *}
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   785
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   786
section {* Formal model of Priority Inheritance \label{model} *}
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   787
text {*
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   788
  \input{../../generated/PrioGDef}
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   789
*}
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   790
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   791
section {* General properties of Priority Inheritance \label{general} *}
264
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   792
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   793
text {*
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   794
  The following are several very basic prioprites:
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   795
  \begin{enumerate}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   796
  \item All runing threads must be ready (@{text "runing_ready"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   797
          @{thm[display] "runing_ready"}  
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   798
  \item All ready threads must be living (@{text "readys_threads"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   799
          @{thm[display] "readys_threads"} 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   800
  \item There are finite many living threads at any moment (@{text "finite_threads"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   801
          @{thm[display] "finite_threads"} 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   802
  \item Every waiting queue does not contain duplcated elements (@{text "wq_distinct"}): 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   803
          @{thm[display] "wq_distinct"} 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   804
  \item All threads in waiting queues are living threads (@{text "wq_threads"}): 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   805
          @{thm[display] "wq_threads"} 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   806
  \item The event which can get a thread into waiting queue must be @{term "P"}-events
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   807
         (@{text "block_pre"}): 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   808
          @{thm[display] "block_pre"}   
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   809
  \item A thread may never wait for two different critical resources
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   810
         (@{text "waiting_unique"}): 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   811
          @{thm[display] waiting_unique[of _ _ "cs\<^isub>1" "cs\<^isub>2"]}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   812
  \item Every resource can only be held by one thread
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   813
         (@{text "held_unique"}): 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   814
          @{thm[display] held_unique[of _ "th\<^isub>1" _ "th\<^isub>2"]}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   815
  \item Every living thread has an unique precedence
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   816
         (@{text "preced_unique"}): 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   817
          @{thm[display] preced_unique[of "th\<^isub>1" _ "th\<^isub>2"]}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   818
  \end{enumerate}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   819
*}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   820
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   821
text {* \noindent
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   822
  The following lemmas show how RAG is changed with the execution of events:
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   823
  \begin{enumerate}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   824
  \item Execution of @{term "Set"} does not change RAG (@{text "depend_set_unchanged"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   825
    @{thm[display] depend_set_unchanged}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   826
  \item Execution of @{term "Create"} does not change RAG (@{text "depend_create_unchanged"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   827
    @{thm[display] depend_create_unchanged}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   828
  \item Execution of @{term "Exit"} does not change RAG (@{text "depend_exit_unchanged"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   829
    @{thm[display] depend_exit_unchanged}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   830
  \item Execution of @{term "P"} (@{text "step_depend_p"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   831
    @{thm[display] step_depend_p}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   832
  \item Execution of @{term "V"} (@{text "step_depend_v"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   833
    @{thm[display] step_depend_v}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   834
  \end{enumerate}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   835
  *}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   836
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   837
text {* \noindent
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   838
  These properties are used to derive the following important results about RAG:
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   839
  \begin{enumerate}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   840
  \item RAG is loop free (@{text "acyclic_depend"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   841
  @{thm [display] acyclic_depend}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   842
  \item RAGs are finite (@{text "finite_depend"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   843
  @{thm [display] finite_depend}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   844
  \item Reverse paths in RAG are well founded (@{text "wf_dep_converse"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   845
  @{thm [display] wf_dep_converse}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   846
  \item The dependence relation represented by RAG has a tree structure (@{text "unique_depend"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   847
  @{thm [display] unique_depend[of _ _ "n\<^isub>1" "n\<^isub>2"]}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   848
  \item All threads in RAG are living threads 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   849
    (@{text "dm_depend_threads"} and @{text "range_in"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   850
    @{thm [display] dm_depend_threads range_in}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   851
  \end{enumerate}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   852
  *}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   853
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   854
text {* \noindent
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   855
  The following lemmas show how every node in RAG can be chased to ready threads:
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   856
  \begin{enumerate}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   857
  \item Every node in RAG can be chased to a ready thread (@{text "chain_building"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   858
    @{thm [display] chain_building[rule_format]}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   859
  \item The ready thread chased to is unique (@{text "dchain_unique"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   860
    @{thm [display] dchain_unique[of _ _ "th\<^isub>1" "th\<^isub>2"]}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   861
  \end{enumerate}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   862
  *}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   863
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   864
text {* \noindent
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   865
  Properties about @{term "next_th"}:
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   866
  \begin{enumerate}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   867
  \item The thread taking over is different from the thread which is releasing
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   868
  (@{text "next_th_neq"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   869
  @{thm [display] next_th_neq}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   870
  \item The thread taking over is unique
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   871
  (@{text "next_th_unique"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   872
  @{thm [display] next_th_unique[of _ _ _ "th\<^isub>1" "th\<^isub>2"]}  
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   873
  \end{enumerate}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   874
  *}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   875
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   876
text {* \noindent
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   877
  Some deeper results about the system:
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   878
  \begin{enumerate}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   879
  \item There can only be one running thread (@{text "runing_unique"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   880
  @{thm [display] runing_unique[of _ "th\<^isub>1" "th\<^isub>2"]}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   881
  \item The maximum of @{term "cp"} and @{term "preced"} are equal (@{text "max_cp_eq"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   882
  @{thm [display] max_cp_eq}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   883
  \item There must be one ready thread having the max @{term "cp"}-value 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   884
  (@{text "max_cp_readys_threads"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   885
  @{thm [display] max_cp_readys_threads}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   886
  \end{enumerate}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   887
  *}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   888
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   889
text {* \noindent
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   890
  The relationship between the count of @{text "P"} and @{text "V"} and the number of 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   891
  critical resources held by a thread is given as follows:
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   892
  \begin{enumerate}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   893
  \item The @{term "V"}-operation decreases the number of critical resources 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   894
    one thread holds (@{text "cntCS_v_dec"})
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   895
     @{thm [display]  cntCS_v_dec}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   896
  \item The number of @{text "V"} never exceeds the number of @{text "P"} 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   897
    (@{text "cnp_cnv_cncs"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   898
    @{thm [display]  cnp_cnv_cncs}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   899
  \item The number of @{text "V"} equals the number of @{text "P"} when 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   900
    the relevant thread is not living:
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   901
    (@{text "cnp_cnv_eq"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   902
    @{thm [display]  cnp_cnv_eq}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   903
  \item When a thread is not living, it does not hold any critical resource 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   904
    (@{text "not_thread_holdents"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   905
    @{thm [display] not_thread_holdents}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   906
  \item When the number of @{text "P"} equals the number of @{text "V"}, the relevant 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   907
    thread does not hold any critical resource, therefore no thread can depend on it
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   908
    (@{text "count_eq_dependents"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   909
    @{thm [display] count_eq_dependents}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   910
  \end{enumerate}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   911
  *}
262
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   912
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   913
section {* Key properties \label{extension} *}
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
   914
264
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   915
(*<*)
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   916
context extend_highest_gen
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   917
begin
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   918
(*>*)
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   919
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   920
text {*
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   921
  The essential of {\em Priority Inheritance} is to avoid indefinite priority inversion. For this 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   922
  purpose, we need to investigate what happens after one thread takes the highest precedence. 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   923
  A locale is used to describe such a situation, which assumes:
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   924
  \begin{enumerate}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   925
  \item @{term "s"} is a valid state (@{text "vt_s"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   926
    @{thm  vt_s}.
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   927
  \item @{term "th"} is a living thread in @{term "s"} (@{text "threads_s"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   928
    @{thm threads_s}.
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   929
  \item @{term "th"} has the highest precedence in @{term "s"} (@{text "highest"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   930
    @{thm highest}.
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   931
  \item The precedence of @{term "th"} is @{term "Prc prio tm"} (@{text "preced_th"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   932
    @{thm preced_th}.
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   933
  \end{enumerate}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   934
  *}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   935
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   936
text {* \noindent
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   937
  Under these assumptions, some basic priority can be derived for @{term "th"}:
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   938
  \begin{enumerate}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   939
  \item The current precedence of @{term "th"} equals its own precedence (@{text "eq_cp_s_th"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   940
    @{thm [display] eq_cp_s_th}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   941
  \item The current precedence of @{term "th"} is the highest precedence in 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   942
    the system (@{text "highest_cp_preced"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   943
    @{thm [display] highest_cp_preced}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   944
  \item The precedence of @{term "th"} is the highest precedence 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   945
    in the system (@{text "highest_preced_thread"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   946
    @{thm [display] highest_preced_thread}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   947
  \item The current precedence of @{term "th"} is the highest current precedence 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   948
    in the system (@{text "highest'"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   949
    @{thm [display] highest'}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   950
  \end{enumerate}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   951
  *}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   952
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   953
text {* \noindent
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   954
  To analysis what happens after state @{term "s"} a sub-locale is defined, which 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   955
  assumes:
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   956
  \begin{enumerate}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   957
  \item @{term "t"} is a valid extension of @{term "s"} (@{text "vt_t"}): @{thm vt_t}.
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   958
  \item Any thread created in @{term "t"} has priority no higher than @{term "prio"}, therefore
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   959
    its precedence can not be higher than @{term "th"},  therefore
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   960
    @{term "th"} remain to be the one with the highest precedence
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   961
    (@{text "create_low"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   962
    @{thm [display] create_low}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   963
  \item Any adjustment of priority in 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   964
    @{term "t"} does not happen to @{term "th"} and 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   965
    the priority set is no higher than @{term "prio"}, therefore
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   966
    @{term "th"} remain to be the one with the highest precedence (@{text "set_diff_low"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   967
    @{thm [display] set_diff_low}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   968
  \item Since we are investigating what happens to @{term "th"}, it is assumed 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   969
    @{term "th"} does not exit during @{term "t"} (@{text "exit_diff"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   970
    @{thm [display] exit_diff}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   971
  \end{enumerate}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   972
*}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   973
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   974
text {* \noindent
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   975
  All these assumptions are put into a predicate @{term "extend_highest_gen"}. 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   976
  It can be proved that @{term "extend_highest_gen"} holds 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   977
  for any moment @{text "i"} in it @{term "t"} (@{text "red_moment"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   978
  @{thm [display] red_moment}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   979
  
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   980
  From this, an induction principle can be derived for @{text "t"}, so that 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   981
  properties already derived for @{term "t"} can be applied to any prefix 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   982
  of @{text "t"} in the proof of new properties 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   983
  about @{term "t"} (@{text "ind"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   984
  \begin{center}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   985
  @{thm[display] ind}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   986
  \end{center}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   987
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   988
  The following properties can be proved about @{term "th"} in @{term "t"}:
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   989
  \begin{enumerate}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   990
  \item In @{term "t"}, thread @{term "th"} is kept live and its 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   991
    precedence is preserved as well
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   992
    (@{text "th_kept"}): 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   993
    @{thm [display] th_kept}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   994
  \item In @{term "t"}, thread @{term "th"}'s precedence is always the maximum among 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   995
    all living threads
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   996
    (@{text "max_preced"}): 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   997
    @{thm [display] max_preced}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   998
  \item In @{term "t"}, thread @{term "th"}'s current precedence is always the maximum precedence
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
   999
    among all living threads
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1000
    (@{text "th_cp_max_preced"}): 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1001
    @{thm [display] th_cp_max_preced}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1002
  \item In @{term "t"}, thread @{term "th"}'s current precedence is always the maximum current 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1003
    precedence among all living threads
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1004
    (@{text "th_cp_max"}): 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1005
    @{thm [display] th_cp_max}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1006
  \item In @{term "t"}, thread @{term "th"}'s current precedence equals its precedence at moment 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1007
    @{term "s"}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1008
    (@{text "th_cp_preced"}): 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1009
    @{thm [display] th_cp_preced}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1010
  \end{enumerate}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1011
  *}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1012
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1013
text {* \noindent
266
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1014
  The main theorem of this part is to characterizing the running thread during @{term "t"} 
264
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1015
  (@{text "runing_inversion_2"}):
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1016
  @{thm [display] runing_inversion_2}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1017
  According to this, if a thread is running, it is either @{term "th"} or was
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1018
  already live and held some resource 
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1019
  at moment @{text "s"} (expressed by: @{text "cntV s th' < cntP s th'"}).
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1020
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1021
  Since there are only finite many threads live and holding some resource at any moment,
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1022
  if every such thread can release all its resources in finite duration, then after finite
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1023
  duration, none of them may block @{term "th"} anymore. So, no priority inversion may happen
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1024
  then.
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1025
  *}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1026
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1027
(*<*)
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1028
end
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1029
(*>*)
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1030
262
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1031
section {* Properties to guide implementation \label{implement} *}
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1032
264
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1033
text {*
266
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1034
  The properties (especially @{text "runing_inversion_2"}) convinced us that the model defined 
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1035
  in Section \ref{model} does prevent indefinite priority inversion and therefore fulfills 
264
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1036
  the fundamental requirement of Priority Inheritance protocol. Another purpose of this paper 
266
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1037
  is to show how this model can be used to guide a concrete implementation. As discussed in
276
a821434474c9 more on intro
urbanc
parents: 275
diff changeset
  1038
  Section 5.6.5 of \cite{Vahalia96}, the implementation of Priority Inheritance in Solaris 
266
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1039
  uses sophisticated linking data structure. Except discussing two scenarios to show how
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1040
  the data structure should be manipulated, a lot of details of the implementation are missing. 
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1041
  In \cite{Faria08,conf/fase/JahierHR09,WellingsBSB07} the protocol is described formally 
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1042
  using different notations, but little information is given on how this protocol can be 
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1043
  implemented efficiently, especially there is no information on how these data structure 
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1044
  should be manipulated. 
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1045
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1046
  Because the scheduling of threads is based on current precedence, 
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1047
  the central issue in implementation of Priority Inheritance is how to compute the precedence
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1048
  correctly and efficiently. As long as the precedence is correct, it is very easy to 
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1049
  modify the scheduling algorithm to select the correct thread to execute. 
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1050
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1051
  First, it can be proved that the computation of current precedence @{term "cp"} of a threads
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1052
  only involves its children (@{text "cp_rec"}):
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1053
  @{thm [display] cp_rec} 
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1054
  where @{term "children s th"} represents the set of children of @{term "th"} in the current
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1055
  RAG: 
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1056
  \[
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1057
  @{thm (lhs) children_def} @{text "\<equiv>"} @{thm (rhs) children_def}
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1058
  \]
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1059
  where the definition of @{term "child"} is: 
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1060
  \[ @{thm (lhs) child_def} @{text "\<equiv>"}  @{thm (rhs) child_def}
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1061
  \]
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1062
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1063
  The aim of this section is to fill the missing details of how current precedence should
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1064
  be changed with the happening of events, with each event type treated by one subsection,
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1065
  where the computation of @{term "cp"} uses lemma @{text "cp_rec"}.
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1066
  *}
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1067
 
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1068
subsection {* Event @{text "Set th prio"} *}
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1069
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1070
(*<*)
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1071
context step_set_cps
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1072
begin
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1073
(*>*)
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1074
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1075
text {*
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1076
  The context under which event @{text "Set th prio"} happens is formalized as follows:
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1077
  \begin{enumerate}
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1078
    \item The formation of @{term "s"} (@{text "s_def"}): @{thm s_def}.
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1079
    \item State @{term "s"} is a valid state (@{text "vt_s"}): @{thm vt_s}. This implies 
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1080
      event @{text "Set th prio"} is eligible to happen under state @{term "s'"} and
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1081
      state @{term "s'"} is a valid state.
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1082
  \end{enumerate}
264
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1083
  *}
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1084
266
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1085
text {* \noindent
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1086
  Under such a context, we investigated how the current precedence @{term "cp"} of 
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1087
  threads change from state @{term "s'"} to @{term "s"} and obtained the following
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1088
  conclusions:
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1089
  \begin{enumerate}
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1090
  %% \item The RAG does not change (@{text "eq_dep"}): @{thm "eq_dep"}.
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1091
  \item All threads with no dependence relation with thread @{term "th"} have their
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1092
    @{term "cp"}-value unchanged (@{text "eq_cp"}):
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1093
    @{thm [display] eq_cp}
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1094
    This lemma implies the @{term "cp"}-value of @{term "th"}
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1095
    and those threads which have a dependence relation with @{term "th"} might need
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1096
    to be recomputed. The way to do this is to start from @{term "th"} 
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1097
    and follow the @{term "depend"}-chain to recompute the @{term "cp"}-value of every 
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1098
    encountered thread using lemma @{text "cp_rec"}. 
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1099
    Since the @{term "depend"}-relation is loop free, this procedure 
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1100
    can always stop. The the following lemma shows this procedure actually could stop earlier.
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1101
  \item The following two lemma shows, if a thread the re-computation of which
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1102
    gives an unchanged @{term "cp"}-value, the procedure described above can stop. 
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1103
    \begin{enumerate}
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1104
      \item Lemma @{text "eq_up_self"} shows if the re-computation of
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1105
        @{term "th"}'s @{term "cp"} gives the same result, the procedure can stop:
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1106
        @{thm [display] eq_up_self}
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1107
      \item Lemma @{text "eq_up"}) shows if the re-computation at intermediate threads
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1108
        gives unchanged result, the procedure can stop:
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1109
        @{thm [display] eq_up}
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1110
  \end{enumerate}
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1111
  \end{enumerate}
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1112
  *}
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1113
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1114
(*<*)
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1115
end
800b0e3b4204 More explanations added by XY.
zhang
parents: 265
diff changeset
  1116
(*>*)
264
24199eb2c423 Newer version.
zhang
parents: 262
diff changeset
  1117
272
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1118
subsection {* Event @{text "V th cs"} *}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1119
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1120
(*<*)
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1121
context step_v_cps_nt
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1122
begin
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1123
(*>*)
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1124
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1125
text {*
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1126
  The context under which event @{text "V th cs"} happens is formalized as follows:
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1127
  \begin{enumerate}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1128
    \item The formation of @{term "s"} (@{text "s_def"}): @{thm s_def}.
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1129
    \item State @{term "s"} is a valid state (@{text "vt_s"}): @{thm vt_s}. This implies 
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1130
      event @{text "V th cs"} is eligible to happen under state @{term "s'"} and
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1131
      state @{term "s'"} is a valid state.
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1132
  \end{enumerate}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1133
  *}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1134
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1135
text {* \noindent
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1136
  Under such a context, we investigated how the current precedence @{term "cp"} of 
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1137
  threads change from state @{term "s'"} to @{term "s"}. 
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1138
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1139
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1140
  Two subcases are considerted, 
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1141
  where the first is that there exits @{term "th'"} 
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1142
  such that 
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1143
  @{thm [display] nt} 
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1144
  holds, which means there exists a thread @{term "th'"} to take over
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1145
  the resource release by thread @{term "th"}. 
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1146
  In this sub-case, the following results are obtained:
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1147
  \begin{enumerate}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1148
  \item The change of RAG is given by lemma @{text "depend_s"}: 
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1149
  @{thm [display] "depend_s"}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1150
  which shows two edges are removed while one is added. These changes imply how
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1151
  the current precedences should be re-computed.
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1152
  \item First all threads different from @{term "th"} and @{term "th'"} have their
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1153
  @{term "cp"}-value kept, therefore do not need a re-computation
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1154
  (@{text "cp_kept"}): @{thm [display] cp_kept}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1155
  This lemma also implies, only the @{term "cp"}-values of @{term "th"} and @{term "th'"}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1156
  need to be recomputed.
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1157
  \end{enumerate}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1158
  *}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1159
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1160
(*<*)
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1161
end
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1162
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1163
context step_v_cps_nnt
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1164
begin
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1165
(*>*)
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1166
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1167
text {*
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1168
  The other sub-case is when for all @{text "th'"}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1169
  @{thm [display] nnt}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1170
  holds, no such thread exists. The following results can be obtained for this 
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1171
  sub-case:
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1172
  \begin{enumerate}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1173
  \item The change of RAG is given by lemma @{text "depend_s"}:
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1174
  @{thm [display] depend_s}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1175
  which means only one edge is removed.
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1176
  \item In this case, no re-computation is needed (@{text "eq_cp"}):
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1177
  @{thm [display] eq_cp}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1178
  \end{enumerate}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1179
  *}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1180
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1181
(*<*)
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1182
end
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1183
(*>*)
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1184
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1185
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1186
subsection {* Event @{text "P th cs"} *}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1187
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1188
(*<*)
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1189
context step_P_cps_e
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1190
begin
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1191
(*>*)
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1192
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1193
text {*
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1194
  The context under which event @{text "P th cs"} happens is formalized as follows:
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1195
  \begin{enumerate}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1196
    \item The formation of @{term "s"} (@{text "s_def"}): @{thm s_def}.
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1197
    \item State @{term "s"} is a valid state (@{text "vt_s"}): @{thm vt_s}. This implies 
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1198
      event @{text "P th cs"} is eligible to happen under state @{term "s'"} and
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1199
      state @{term "s'"} is a valid state.
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1200
  \end{enumerate}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1201
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1202
  This case is further divided into two sub-cases. The first is when @{thm ee} holds.
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1203
  The following results can be obtained:
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1204
  \begin{enumerate}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1205
  \item One edge is added to the RAG (@{text "depend_s"}):
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1206
    @{thm [display] depend_s}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1207
  \item No re-computation is needed (@{text "eq_cp"}):
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1208
    @{thm [display] eq_cp}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1209
  \end{enumerate}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1210
*}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1211
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1212
(*<*)
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1213
end
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1214
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1215
context step_P_cps_ne
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1216
begin
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1217
(*>*)
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1218
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1219
text {*
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1220
  The second is when @{thm ne} holds.
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1221
  The following results can be obtained:
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1222
  \begin{enumerate}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1223
  \item One edge is added to the RAG (@{text "depend_s"}):
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1224
    @{thm [display] depend_s}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1225
  \item Threads with no dependence relation with @{term "th"} do not need a re-computation
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1226
    of their @{term "cp"}-values (@{text "eq_cp"}):
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1227
    @{thm [display] eq_cp}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1228
    This lemma implies all threads with a dependence relation with @{term "th"} may need 
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1229
    re-computation.
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1230
  \item Similar to the case of @{term "Set"}, the computation procedure could stop earlier
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1231
    (@{text "eq_up"}):
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1232
    @{thm [display] eq_up}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1233
  \end{enumerate}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1234
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1235
  *}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1236
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1237
(*<*)
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1238
end
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1239
(*>*)
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1240
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1241
subsection {* Event @{text "Create th prio"} *}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1242
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1243
(*<*)
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1244
context step_create_cps
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1245
begin
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1246
(*>*)
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1247
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1248
text {*
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1249
  The context under which event @{text "Create th prio"} happens is formalized as follows:
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1250
  \begin{enumerate}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1251
    \item The formation of @{term "s"} (@{text "s_def"}): @{thm s_def}.
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1252
    \item State @{term "s"} is a valid state (@{text "vt_s"}): @{thm vt_s}. This implies 
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1253
      event @{text "Create th prio"} is eligible to happen under state @{term "s'"} and
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1254
      state @{term "s'"} is a valid state.
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1255
  \end{enumerate}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1256
  The following results can be obtained under this context:
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1257
  \begin{enumerate}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1258
  \item The RAG does not change (@{text "eq_dep"}):
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1259
    @{thm [display] eq_dep}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1260
  \item All threads other than @{term "th"} do not need re-computation (@{text "eq_cp"}):
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1261
    @{thm [display] eq_cp}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1262
  \item The @{term "cp"}-value of @{term "th"} equals its precedence 
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1263
    (@{text "eq_cp_th"}):
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1264
    @{thm [display] eq_cp_th}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1265
  \end{enumerate}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1266
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1267
*}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1268
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1269
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1270
(*<*)
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1271
end
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1272
(*>*)
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1273
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1274
subsection {* Event @{text "Exit th"} *}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1275
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1276
(*<*)
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1277
context step_exit_cps
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1278
begin
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1279
(*>*)
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1280
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1281
text {*
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1282
  The context under which event @{text "Exit th"} happens is formalized as follows:
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1283
  \begin{enumerate}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1284
    \item The formation of @{term "s"} (@{text "s_def"}): @{thm s_def}.
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1285
    \item State @{term "s"} is a valid state (@{text "vt_s"}): @{thm vt_s}. This implies 
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1286
      event @{text "Exit th"} is eligible to happen under state @{term "s'"} and
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1287
      state @{term "s'"} is a valid state.
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1288
  \end{enumerate}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1289
  The following results can be obtained under this context:
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1290
  \begin{enumerate}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1291
  \item The RAG does not change (@{text "eq_dep"}):
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1292
    @{thm [display] eq_dep}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1293
  \item All threads other than @{term "th"} do not need re-computation (@{text "eq_cp"}):
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1294
    @{thm [display] eq_cp}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1295
  \end{enumerate}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1296
  Since @{term th} does not live in state @{term "s"}, there is no need to compute 
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1297
  its @{term cp}-value.
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1298
*}
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1299
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1300
(*<*)
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1301
end
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1302
(*>*)
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1303
ee4611c1e13c All comments added.
zhang
parents: 271
diff changeset
  1304
262
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1305
section {* Related works \label{related} *}
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1306
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1307
text {*
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1308
  \begin{enumerate}
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1309
  \item {\em Integrating Priority Inheritance Algorithms in the Real-Time Specification for Java}
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1310
    \cite{WellingsBSB07} models and verifies the combination of Priority Inheritance (PI) and 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1311
    Priority Ceiling Emulation (PCE) protocols in the setting of Java virtual machine 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1312
    using extended Timed Automata(TA) formalism of the UPPAAL tool. Although a detailed 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1313
    formal model of combined PI and PCE is given, the number of properties is quite 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1314
    small and the focus is put on the harmonious working of PI and PCE. Most key features of PI 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1315
    (as well as PCE) are not shown. Because of the limitation of the model checking technique
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1316
    used there, properties are shown only for a small number of scenarios. Therefore, 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1317
    the verification does not show the correctness of the formal model itself in a 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1318
    convincing way.  
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1319
  \item {\em Formal Development of Solutions for Real-Time Operating Systems with TLA+/TLC}
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1320
    \cite{Faria08}. A formal model of PI is given in TLA+. Only 3 properties are shown 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1321
    for PI using model checking. The limitation of model checking is intrinsic to the work.
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1322
  \item {\em Synchronous modeling and validation of priority inheritance schedulers}
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1323
    \cite{conf/fase/JahierHR09}. Gives a formal model
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1324
    of PI and PCE in AADL (Architecture Analysis \& Design Language) and checked 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1325
    several properties using model checking. The number of properties shown there is 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1326
    less than here and the scale is also limited by the model checking technique. 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1327
  \item {\em The Priority Ceiling Protocol: Formalization and Analysis Using PVS}
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1328
    \cite{dutertre99b}. Formalized another protocol for Priority Inversion in the 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1329
    interactive theorem proving system PVS.
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1330
\end{enumerate}
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1331
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1332
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1333
  There are several works on inversion avoidance:
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1334
  \begin{enumerate}
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1335
  \item {\em Solving the group priority inversion problem in a timed asynchronous system}
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1336
    \cite{Wang:2002:SGP}. The notion of Group Priority Inversion is introduced. The main 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1337
    strategy is still inversion avoidance. The method is by reordering requests 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1338
    in the setting of Client-Server.
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1339
  \item {\em A Formalization of Priority Inversion} \cite{journals/rts/BabaogluMS93}. 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1340
    Formalized the notion of Priority 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1341
    Inversion and proposes methods to avoid it. 
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1342
  \end{enumerate}
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1343
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1344
  {\em Examples of inaccurate specification of the protocol ???}.
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1345
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1346
*}
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1347
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1348
section {* Conclusions \label{conclusion} *}
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1349
286
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1350
text {*
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1351
  The work in this paper only deals with single CPU configurations. The
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1352
  "one CPU" assumption is essential for our formalisation, because the
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1353
  main lemma fails in multi-CPU configuration. The lemma says that any
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1354
  runing thead must be the one with the highest prioirty or already held
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1355
  some resource when the highest priority thread was initiated. When
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1356
  there are multiple CPUs, it may well be the case that a threads did
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1357
  not hold any resource when the highest priority thread was initiated,
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1358
  but that thread still runs after that moment on a separate CPU. In
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1359
  this way, the main lemma does not hold anymore.
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1360
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1361
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1362
  There are some works deals with priority inversion in multi-CPU
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1363
  configurations[???], but none of them have given a formal correctness
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1364
  proof. The extension of our formal proof to deal with multi-CPU
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1365
  configurations is not obvious. One possibility, as suggested in paper
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1366
  [???], is change our formal model (the defiintion of "schs") to give
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1367
  the released resource to the thread with the highest prioirty. In this
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1368
  way, indefinite prioirty inversion can be avoided, but for a quite
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1369
  different reason from the one formalized in this paper (because the
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1370
  "mail lemma" will be different). This means a formal correctness proof
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1371
  for milt-CPU configuration would be quite different from the one given
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1372
  in this paper. The solution of prioirty inversion problem in mult-CPU
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1373
  configurations is a different problem which needs different solutions
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1374
  which is outside the scope of this paper.
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1375
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1376
*}
572f202659ff corrections by Xingyuan
urbanc
parents: 285
diff changeset
  1377
262
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1378
(*<*)
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1379
end
4190df6f4488 initial version of the PIP formalisation
urbanc
parents:
diff changeset
  1380
(*>*)