| 262 |      1 | (*<*)
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|  |      2 | theory Paper
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| 272 |      3 | imports CpsG ExtGG (* "~~/src/HOL/Library/LaTeXsugar" *) LaTeXsugar
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| 262 |      4 | begin
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| 266 |      5 | ML {*
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| 273 |      6 |   open Printer;
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| 272 |      7 |   show_question_marks_default := false;
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| 266 |      8 |   *}
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| 262 |      9 | (*>*)
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|  |     10 | 
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|  |     11 | section {* Introduction *}
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|  |     12 | 
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|  |     13 | text {*
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| 273 |     14 |   Many real-time systems need to support processes with priorities and
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| 267 |     15 |   locking of resources. Locking of resources ensures mutual exclusion
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| 275 |     16 |   when accessing shared data or devices that cannot be
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|  |     17 |   preempted. Priorities allow scheduling of processes that need to
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|  |     18 |   finish their work within deadlines.  Unfortunately, both features
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|  |     19 |   can interact in subtle ways leading to a problem, called
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|  |     20 |   \emph{Priority Inversion}. Suppose three processes having priorities
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|  |     21 |   $H$(igh), $M$(edium) and $L$(ow). We would expect that the process
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|  |     22 |   $H$ blocks any other process with lower priority and itself cannot
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|  |     23 |   be blocked by any process with lower priority. Alas, in a naive
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|  |     24 |   implementation of resource looking and priorities this property can
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|  |     25 |   be violated. Even worse, $H$ can be delayed indefinitely by
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|  |     26 |   processes with lower priorities. For this let $L$ be in the
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|  |     27 |   possession of a lock for a resource that also $H$ needs. $H$ must
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|  |     28 |   therefore wait for $L$ to exit the critical section and release this
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|  |     29 |   lock. The problem is that $L$ might in turn be blocked by any
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|  |     30 |   process with priority $M$, and so $H$ sits there potentially waiting
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|  |     31 |   indefinitely. Since $H$ is blocked by processes with lower
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|  |     32 |   priorities, the problem is called Priority Inversion. It was first
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|  |     33 |   described in \cite{Lampson:Redell:cacm:1980} in the context of the
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|  |     34 |   Mesa programming language designed for concurrent programming.
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| 265 |     35 | 
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| 273 |     36 |   If the problem of Priority Inversion is ignored, real-time systems
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| 267 |     37 |   can become unpredictable and resulting bugs can be hard to diagnose.
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|  |     38 |   The classic example where this happened is the software that
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| 268 |     39 |   controlled the Mars Pathfinder mission in 1997
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|  |     40 |   \cite{Reeves-Glenn-1998}.  Once the spacecraft landed, the software
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| 275 |     41 |   shut down at irregular intervals leading to loss of project time as
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| 268 |     42 |   normal operation of the craft could only resume the next day (the
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| 270 |     43 |   mission and data already collected were fortunately not lost, because
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| 268 |     44 |   of a clever system design).  The reason for the shutdowns was that
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| 271 |     45 |   the scheduling software fell victim of Priority Inversion: a low
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| 268 |     46 |   priority task locking a resource prevented a high priority process
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| 270 |     47 |   from running in time leading to a system reset. Once the problem was found,
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| 275 |     48 |   it was rectified by enabling the \emph{Priority Inheritance Protocol} 
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|  |     49 |   (PIP) \cite{journals/tc/ShaRL90} in the scheduling software.
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| 262 |     50 | 
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| 275 |     51 |   The idea behind PIP is to let the process $L$ temporarily
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|  |     52 |   inherit the high priority from $H$ until $L$ leaves the critical
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|  |     53 |   section unlocking the resource. This solves the problem of $H$
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|  |     54 |   having to wait indefinitely, because $L$ cannot, for example, be
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|  |     55 |   blocked by processes having priority $M$. While a few other
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|  |     56 |   solutions exist for the Priority Inversion problem
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|  |     57 |   \cite{Lampson:Redell:cacm:1980}, PIP is one that is widely deployed
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|  |     58 |   and implemented. This includes VxWorks (a proprietary real-time OS
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|  |     59 |   used in the Mars Pathfinder mission, in Boeing's 787 Dreamliner,
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|  |     60 |   Honda's ASIMO robot, etc.), but also the POSIX 1003.1c Standard
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|  |     61 |   realised for example in libraries for FreeBSD, Solaris and Linux.
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| 274 |     62 | 
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| 275 |     63 |   One advantage of PIP is that increasing the priority of a process
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|  |     64 |   can be dynamically calculated by the scheduler. This is in contrast
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|  |     65 |   to, for example, \emph{Priority Ceiling}, another solution to the
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|  |     66 |   Priority Inversion problem, which requires static analysis of the
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|  |     67 |   program in order to be helpful. However, there has also been strong
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|  |     68 |   criticism against PIP. For instance, PIP cannot prevent deadlocks,
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|  |     69 |   and also blocking times can be substantial (more than just the
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|  |     70 |   duration of a critical section).  Though, most criticism against PIP
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|  |     71 |   centres around unreliable implementations and around PIP being
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|  |     72 |   too complicated and too inefficient.  For example, Yodaiken writes in \cite{Yodaiken02}:
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| 274 |     73 | 
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|  |     74 |   \begin{quote}
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|  |     75 |   \it{}``Priority inheritance is neither efficient nor reliable. Implementations
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|  |     76 |   are either incomplete (and unreliable) or surprisingly complex and intrusive.''
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|  |     77 |   \end{quote}
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| 273 |     78 | 
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| 274 |     79 |   \noindent
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| 275 |     80 |   He suggests to avoid PIP altogether by not allowing critical
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|  |     81 |   sections to be preempted. While this was a sensible solution in
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|  |     82 |   2002, in our modern multiprocessor world, this seems out of date.
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|  |     83 |   However, there is clearly a need for investigating correct and
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|  |     84 |   efficient algorithms for PIP. A few specifications for PIP exist (in
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|  |     85 |   English) and also a few high-level descriptions of implementations
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|  |     86 |   (e.g.~in the textbook \cite[Section 5.6.5]{Vahalia96}), but they help little with
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|  |     87 |   actual implementations. That this is a problem in practise is proved
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|  |     88 |   by an email from Baker, who wrote on 13 July 2009 on the Linux
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|  |     89 |   Kernel mailing list:
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| 274 |     90 | 
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|  |     91 |   \begin{quote}
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| 275 |     92 |   \it{}``I observed in the kernel code (to my disgust), the Linux PIP
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|  |     93 |   implementation is a nightmare: extremely heavy weight, involving
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|  |     94 |   maintenance of a full wait-for graph, and requiring updates for a
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|  |     95 |   range of events, including priority changes and interruptions of
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|  |     96 |   wait operations.''
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| 274 |     97 |   \end{quote}
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|  |     98 | 
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|  |     99 |   \noindent
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|  |    100 |   This however means it is useful to look at PIP again from a more
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| 275 |    101 |   abstract level (but still concrete enough to inform an
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|  |    102 |   implementation) and makes PIP an ideal candidate for a formal
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|  |    103 |   verification. One reason, of course, is that the original
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|  |    104 |   presentation of PIP, despite being informally ``proved'' correct, is
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|  |    105 |   flawed. Yodaiken \cite{Yodaiken02} points to a subtlety that has
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|  |    106 |   been overlooked by Sha et al.
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| 274 |    107 | 
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| 275 |    108 |   But this is too
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|  |    109 |   simplistic. Consider
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| 273 |    110 |   Priority Inversion problem has been known since 1980
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|  |    111 |   \cite{Lampson:Redell:cacm:1980}, but Sha et al.~give the first
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|  |    112 |   thorough analysis and present an informal correctness proof for PIP
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|  |    113 |   .\footnote{Sha et al.~call it the
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|  |    114 |   \emph{Basic Priority Inheritance Protocol}.}
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| 267 |    115 | 
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| 274 |    116 |    POSIX.4: programming for the real world (Google eBook)
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|  |    117 | 
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| 267 |    118 |   However, there are further subtleties: just lowering the priority 
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|  |    119 |   of the process $L$ to its low priority, as proposed in ???, is 
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|  |    120 |   incorrect.\bigskip
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| 273 |    121 | 
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| 274 |    122 |   
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| 273 |    123 | 
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| 274 |    124 |   very little on implementations, not to mention implementations informed by 
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|  |    125 |   formal correctness proofs.
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|  |    126 | 
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| 267 |    127 |   
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|  |    128 |   \noindent
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| 262 |    129 |   Priority inversion referrers to the phenomena where tasks with higher 
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|  |    130 |   priority are blocked by ones with lower priority. If priority inversion 
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|  |    131 |   is not controlled, there will be no guarantee the urgent tasks will be 
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|  |    132 |   processed in time. As reported in \cite{Reeves-Glenn-1998}, 
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|  |    133 |   priority inversion used to cause software system resets and data lose in 
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|  |    134 |   JPL's Mars pathfinder project. Therefore, the avoiding, detecting and controlling 
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|  |    135 |   of priority inversion is a key issue to attain predictability in priority 
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|  |    136 |   based real-time systems. 
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|  |    137 | 
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|  |    138 |   The priority inversion phenomenon was first published in \cite{Lampson:Redell:cacm:1980}. 
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|  |    139 |   The two protocols widely used to eliminate priority inversion, namely 
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|  |    140 |   PI (Priority Inheritance) and PCE (Priority Ceiling Emulation), were proposed 
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|  |    141 |   in \cite{journals/tc/ShaRL90}. PCE is less convenient to use because it requires 
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|  |    142 |   static analysis of programs. Therefore, PI is more commonly used in 
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|  |    143 |   practice\cite{locke-july02}. However, as pointed out in the literature, 
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|  |    144 |   the analysis of priority inheritance protocol is quite subtle\cite{yodaiken-july02}. 
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|  |    145 |   A formal analysis will certainly be helpful for us to understand and correctly 
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|  |    146 |   implement PI. All existing formal analysis of PI
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|  |    147 |   \cite{conf/fase/JahierHR09,WellingsBSB07,Faria08} are based on the model checking 
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|  |    148 |   technology. Because of the state explosion problem, model check 
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|  |    149 |   is much like an exhaustive testing of finite models with limited size. 
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|  |    150 |   The results obtained can not be safely generalized to models with arbitrarily 
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|  |    151 |   large size. Worse still, since model checking is fully automatic, it give little 
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|  |    152 |   insight on why the formal model is correct. It is therefore 
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|  |    153 |   definitely desirable to analyze PI using theorem proving, which gives 
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|  |    154 |   more general results as well as deeper insight. And this is the purpose 
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|  |    155 |   of this paper which gives a formal analysis of PI in the interactive 
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|  |    156 |   theorem prover Isabelle using Higher Order Logic (HOL). The formalization 
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|  |    157 |   focuses on on two issues:
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|  |    158 | 
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|  |    159 |   \begin{enumerate}
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|  |    160 |   \item The correctness of the protocol model itself. A series of desirable properties is 
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|  |    161 |     derived until we are fully convinced that the formal model of PI does 
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|  |    162 |     eliminate priority inversion. And a better understanding of PI is so obtained 
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|  |    163 |     in due course. For example, we find through formalization that the choice of 
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|  |    164 |     next thread to take hold when a 
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|  |    165 |     resource is released is irrelevant for the very basic property of PI to hold. 
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|  |    166 |     A point never mentioned in literature. 
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|  |    167 |   \item The correctness of the implementation. A series of properties is derived the meaning 
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|  |    168 |     of which can be used as guidelines on how PI can be implemented efficiently and correctly. 
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|  |    169 |   \end{enumerate} 
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|  |    170 | 
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|  |    171 |   The rest of the paper is organized as follows: Section \ref{overview} gives an overview 
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|  |    172 |   of PI. Section \ref{model} introduces the formal model of PI. Section \ref{general} 
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|  |    173 |   discusses a series of basic properties of PI. Section \ref{extension} shows formally 
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|  |    174 |   how priority inversion is controlled by PI. Section \ref{implement} gives properties 
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|  |    175 |   which can be used for guidelines of implementation. Section \ref{related} discusses 
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|  |    176 |   related works. Section \ref{conclusion} concludes the whole paper.
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| 265 |    177 | 
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| 273 |    178 |   The basic priority inheritance protocol has two problems:
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|  |    179 | 
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|  |    180 |   It does not prevent a deadlock from happening in a program with circular lock dependencies.
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|  |    181 |   
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|  |    182 |   A chain of blocking may be formed; blocking duration can be substantial, though bounded.
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|  |    183 | 
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| 265 |    184 | 
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|  |    185 |   Contributions
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|  |    186 | 
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|  |    187 |   Despite the wide use of Priority Inheritance Protocol in real time operating
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|  |    188 |   system, it's correctness has never been formally proved and mechanically checked. 
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|  |    189 |   All existing verification are based on model checking technology. Full automatic
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|  |    190 |   verification gives little help to understand why the protocol is correct. 
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|  |    191 |   And results such obtained only apply to models of limited size. 
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|  |    192 |   This paper presents a formal verification based on theorem proving. 
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|  |    193 |   Machine checked formal proof does help to get deeper understanding. We found 
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|  |    194 |   the fact which is not mentioned in the literature, that the choice of next 
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|  |    195 |   thread to take over when an critical resource is release does not affect the correctness
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|  |    196 |   of the protocol. The paper also shows how formal proof can help to construct 
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|  |    197 |   correct and efficient implementation.\bigskip 
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|  |    198 | 
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| 262 |    199 | *}
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|  |    200 | 
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|  |    201 | section {* An overview of priority inversion and priority inheritance \label{overview} *}
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|  |    202 | 
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|  |    203 | text {*
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|  |    204 | 
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|  |    205 |   Priority inversion refers to the phenomenon when a thread with high priority is blocked 
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|  |    206 |   by a thread with low priority. Priority happens when the high priority thread requests 
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|  |    207 |   for some critical resource already taken by the low priority thread. Since the high 
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|  |    208 |   priority thread has to wait for the low priority thread to complete, it is said to be 
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|  |    209 |   blocked by the low priority thread. Priority inversion might prevent high priority 
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|  |    210 |   thread from fulfill its task in time if the duration of priority inversion is indefinite 
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|  |    211 |   and unpredictable. Indefinite priority inversion happens when indefinite number 
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|  |    212 |   of threads with medium priorities is activated during the period when the high 
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|  |    213 |   priority thread is blocked by the low priority thread. Although these medium 
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|  |    214 |   priority threads can not preempt the high priority thread directly, they are able 
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|  |    215 |   to preempt the low priority threads and cause it to stay in critical section for 
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|  |    216 |   an indefinite long duration. In this way, the high priority thread may be blocked indefinitely. 
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|  |    217 |   
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|  |    218 |   Priority inheritance is one protocol proposed to avoid indefinite priority inversion. 
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|  |    219 |   The basic idea is to let the high priority thread donate its priority to the low priority 
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|  |    220 |   thread holding the critical resource, so that it will not be preempted by medium priority 
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|  |    221 |   threads. The thread with highest priority will not be blocked unless it is requesting 
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|  |    222 |   some critical resource already taken by other threads. Viewed from a different angle, 
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|  |    223 |   any thread which is able to block the highest priority threads must already hold some 
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|  |    224 |   critical resource. Further more, it must have hold some critical resource at the 
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|  |    225 |   moment the highest priority is created, otherwise, it may never get change to run and 
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|  |    226 |   get hold. Since the number of such resource holding lower priority threads is finite, 
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|  |    227 |   if every one of them finishes with its own critical section in a definite duration, 
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|  |    228 |   the duration the highest priority thread is blocked is definite as well. The key to 
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|  |    229 |   guarantee lower priority threads to finish in definite is to donate them the highest 
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|  |    230 |   priority. In such cases, the lower priority threads is said to have inherited the 
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|  |    231 |   highest priority. And this explains the name of the protocol: 
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|  |    232 |   {\em Priority Inheritance} and how Priority Inheritance prevents indefinite delay.
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|  |    233 | 
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|  |    234 |   The objectives of this paper are:
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|  |    235 |   \begin{enumerate}
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|  |    236 |   \item Build the above mentioned idea into formal model and prove a series of properties 
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|  |    237 |     until we are convinced that the formal model does fulfill the original idea. 
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|  |    238 |   \item Show how formally derived properties can be used as guidelines for correct 
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|  |    239 |     and efficient implementation.
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|  |    240 |   \end{enumerate}
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|  |    241 |   The proof is totally formal in the sense that every detail is reduced to the 
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|  |    242 |   very first principles of Higher Order Logic. The nature of interactive theorem 
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|  |    243 |   proving is for the human user to persuade computer program to accept its arguments. 
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|  |    244 |   A clear and simple understanding of the problem at hand is both a prerequisite and a 
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|  |    245 |   byproduct of such an effort, because everything has finally be reduced to the very 
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|  |    246 |   first principle to be checked mechanically. The former intuitive explanation of 
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|  |    247 |   Priority Inheritance is just such a byproduct. 
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|  |    248 |   *}
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|  |    249 | 
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|  |    250 | section {* Formal model of Priority Inheritance \label{model} *}
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|  |    251 | text {*
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|  |    252 |   \input{../../generated/PrioGDef}
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|  |    253 | *}
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|  |    254 | 
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|  |    255 | section {* General properties of Priority Inheritance \label{general} *}
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| 264 |    256 | 
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|  |    257 | text {*
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|  |    258 |   The following are several very basic prioprites:
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|  |    259 |   \begin{enumerate}
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|  |    260 |   \item All runing threads must be ready (@{text "runing_ready"}):
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|  |    261 |           @{thm[display] "runing_ready"}  
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|  |    262 |   \item All ready threads must be living (@{text "readys_threads"}):
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|  |    263 |           @{thm[display] "readys_threads"} 
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|  |    264 |   \item There are finite many living threads at any moment (@{text "finite_threads"}):
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|  |    265 |           @{thm[display] "finite_threads"} 
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|  |    266 |   \item Every waiting queue does not contain duplcated elements (@{text "wq_distinct"}): 
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|  |    267 |           @{thm[display] "wq_distinct"} 
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|  |    268 |   \item All threads in waiting queues are living threads (@{text "wq_threads"}): 
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|  |    269 |           @{thm[display] "wq_threads"} 
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|  |    270 |   \item The event which can get a thread into waiting queue must be @{term "P"}-events
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|  |    271 |          (@{text "block_pre"}): 
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|  |    272 |           @{thm[display] "block_pre"}   
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|  |    273 |   \item A thread may never wait for two different critical resources
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|  |    274 |          (@{text "waiting_unique"}): 
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|  |    275 |           @{thm[display] waiting_unique[of _ _ "cs\<^isub>1" "cs\<^isub>2"]}
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|  |    276 |   \item Every resource can only be held by one thread
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|  |    277 |          (@{text "held_unique"}): 
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|  |    278 |           @{thm[display] held_unique[of _ "th\<^isub>1" _ "th\<^isub>2"]}
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|  |    279 |   \item Every living thread has an unique precedence
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|  |    280 |          (@{text "preced_unique"}): 
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|  |    281 |           @{thm[display] preced_unique[of "th\<^isub>1" _ "th\<^isub>2"]}
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|  |    282 |   \end{enumerate}
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|  |    283 | *}
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|  |    284 | 
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|  |    285 | text {* \noindent
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|  |    286 |   The following lemmas show how RAG is changed with the execution of events:
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|  |    287 |   \begin{enumerate}
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|  |    288 |   \item Execution of @{term "Set"} does not change RAG (@{text "depend_set_unchanged"}):
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|  |    289 |     @{thm[display] depend_set_unchanged}
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|  |    290 |   \item Execution of @{term "Create"} does not change RAG (@{text "depend_create_unchanged"}):
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|  |    291 |     @{thm[display] depend_create_unchanged}
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|  |    292 |   \item Execution of @{term "Exit"} does not change RAG (@{text "depend_exit_unchanged"}):
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|  |    293 |     @{thm[display] depend_exit_unchanged}
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|  |    294 |   \item Execution of @{term "P"} (@{text "step_depend_p"}):
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|  |    295 |     @{thm[display] step_depend_p}
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|  |    296 |   \item Execution of @{term "V"} (@{text "step_depend_v"}):
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|  |    297 |     @{thm[display] step_depend_v}
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|  |    298 |   \end{enumerate}
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|  |    299 |   *}
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|  |    300 | 
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|  |    301 | text {* \noindent
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|  |    302 |   These properties are used to derive the following important results about RAG:
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|  |    303 |   \begin{enumerate}
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|  |    304 |   \item RAG is loop free (@{text "acyclic_depend"}):
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|  |    305 |   @{thm [display] acyclic_depend}
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|  |    306 |   \item RAGs are finite (@{text "finite_depend"}):
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|  |    307 |   @{thm [display] finite_depend}
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|  |    308 |   \item Reverse paths in RAG are well founded (@{text "wf_dep_converse"}):
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|  |    309 |   @{thm [display] wf_dep_converse}
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|  |    310 |   \item The dependence relation represented by RAG has a tree structure (@{text "unique_depend"}):
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|  |    311 |   @{thm [display] unique_depend[of _ _ "n\<^isub>1" "n\<^isub>2"]}
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|  |    312 |   \item All threads in RAG are living threads 
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|  |    313 |     (@{text "dm_depend_threads"} and @{text "range_in"}):
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|  |    314 |     @{thm [display] dm_depend_threads range_in}
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|  |    315 |   \end{enumerate}
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|  |    316 |   *}
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|  |    317 | 
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|  |    318 | text {* \noindent
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|  |    319 |   The following lemmas show how every node in RAG can be chased to ready threads:
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|  |    320 |   \begin{enumerate}
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|  |    321 |   \item Every node in RAG can be chased to a ready thread (@{text "chain_building"}):
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|  |    322 |     @{thm [display] chain_building[rule_format]}
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|  |    323 |   \item The ready thread chased to is unique (@{text "dchain_unique"}):
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|  |    324 |     @{thm [display] dchain_unique[of _ _ "th\<^isub>1" "th\<^isub>2"]}
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|  |    325 |   \end{enumerate}
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|  |    326 |   *}
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|  |    327 | 
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|  |    328 | text {* \noindent
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|  |    329 |   Properties about @{term "next_th"}:
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|  |    330 |   \begin{enumerate}
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|  |    331 |   \item The thread taking over is different from the thread which is releasing
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|  |    332 |   (@{text "next_th_neq"}):
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|  |    333 |   @{thm [display] next_th_neq}
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|  |    334 |   \item The thread taking over is unique
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|  |    335 |   (@{text "next_th_unique"}):
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|  |    336 |   @{thm [display] next_th_unique[of _ _ _ "th\<^isub>1" "th\<^isub>2"]}  
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|  |    337 |   \end{enumerate}
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|  |    338 |   *}
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|  |    339 | 
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|  |    340 | text {* \noindent
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|  |    341 |   Some deeper results about the system:
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|  |    342 |   \begin{enumerate}
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|  |    343 |   \item There can only be one running thread (@{text "runing_unique"}):
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|  |    344 |   @{thm [display] runing_unique[of _ "th\<^isub>1" "th\<^isub>2"]}
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|  |    345 |   \item The maximum of @{term "cp"} and @{term "preced"} are equal (@{text "max_cp_eq"}):
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|  |    346 |   @{thm [display] max_cp_eq}
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|  |    347 |   \item There must be one ready thread having the max @{term "cp"}-value 
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|  |    348 |   (@{text "max_cp_readys_threads"}):
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|  |    349 |   @{thm [display] max_cp_readys_threads}
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|  |    350 |   \end{enumerate}
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|  |    351 |   *}
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|  |    352 | 
 | 
|  |    353 | text {* \noindent
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|  |    354 |   The relationship between the count of @{text "P"} and @{text "V"} and the number of 
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|  |    355 |   critical resources held by a thread is given as follows:
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|  |    356 |   \begin{enumerate}
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|  |    357 |   \item The @{term "V"}-operation decreases the number of critical resources 
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|  |    358 |     one thread holds (@{text "cntCS_v_dec"})
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|  |    359 |      @{thm [display]  cntCS_v_dec}
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|  |    360 |   \item The number of @{text "V"} never exceeds the number of @{text "P"} 
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|  |    361 |     (@{text "cnp_cnv_cncs"}):
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|  |    362 |     @{thm [display]  cnp_cnv_cncs}
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|  |    363 |   \item The number of @{text "V"} equals the number of @{text "P"} when 
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|  |    364 |     the relevant thread is not living:
 | 
|  |    365 |     (@{text "cnp_cnv_eq"}):
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|  |    366 |     @{thm [display]  cnp_cnv_eq}
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|  |    367 |   \item When a thread is not living, it does not hold any critical resource 
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|  |    368 |     (@{text "not_thread_holdents"}):
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|  |    369 |     @{thm [display] not_thread_holdents}
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|  |    370 |   \item When the number of @{text "P"} equals the number of @{text "V"}, the relevant 
 | 
|  |    371 |     thread does not hold any critical resource, therefore no thread can depend on it
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|  |    372 |     (@{text "count_eq_dependents"}):
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|  |    373 |     @{thm [display] count_eq_dependents}
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|  |    374 |   \end{enumerate}
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|  |    375 |   *}
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| 262 |    376 | 
 | 
|  |    377 | section {* Key properties \label{extension} *}
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|  |    378 | 
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| 264 |    379 | (*<*)
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|  |    380 | context extend_highest_gen
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|  |    381 | begin
 | 
|  |    382 | (*>*)
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|  |    383 | 
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|  |    384 | text {*
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|  |    385 |   The essential of {\em Priority Inheritance} is to avoid indefinite priority inversion. For this 
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|  |    386 |   purpose, we need to investigate what happens after one thread takes the highest precedence. 
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|  |    387 |   A locale is used to describe such a situation, which assumes:
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|  |    388 |   \begin{enumerate}
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|  |    389 |   \item @{term "s"} is a valid state (@{text "vt_s"}):
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|  |    390 |     @{thm  vt_s}.
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|  |    391 |   \item @{term "th"} is a living thread in @{term "s"} (@{text "threads_s"}):
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|  |    392 |     @{thm threads_s}.
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|  |    393 |   \item @{term "th"} has the highest precedence in @{term "s"} (@{text "highest"}):
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|  |    394 |     @{thm highest}.
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|  |    395 |   \item The precedence of @{term "th"} is @{term "Prc prio tm"} (@{text "preced_th"}):
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|  |    396 |     @{thm preced_th}.
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|  |    397 |   \end{enumerate}
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|  |    398 |   *}
 | 
|  |    399 | 
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|  |    400 | text {* \noindent
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|  |    401 |   Under these assumptions, some basic priority can be derived for @{term "th"}:
 | 
|  |    402 |   \begin{enumerate}
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|  |    403 |   \item The current precedence of @{term "th"} equals its own precedence (@{text "eq_cp_s_th"}):
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|  |    404 |     @{thm [display] eq_cp_s_th}
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|  |    405 |   \item The current precedence of @{term "th"} is the highest precedence in 
 | 
|  |    406 |     the system (@{text "highest_cp_preced"}):
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|  |    407 |     @{thm [display] highest_cp_preced}
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|  |    408 |   \item The precedence of @{term "th"} is the highest precedence 
 | 
|  |    409 |     in the system (@{text "highest_preced_thread"}):
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|  |    410 |     @{thm [display] highest_preced_thread}
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|  |    411 |   \item The current precedence of @{term "th"} is the highest current precedence 
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|  |    412 |     in the system (@{text "highest'"}):
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|  |    413 |     @{thm [display] highest'}
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|  |    414 |   \end{enumerate}
 | 
|  |    415 |   *}
 | 
|  |    416 | 
 | 
|  |    417 | text {* \noindent
 | 
|  |    418 |   To analysis what happens after state @{term "s"} a sub-locale is defined, which 
 | 
|  |    419 |   assumes:
 | 
|  |    420 |   \begin{enumerate}
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|  |    421 |   \item @{term "t"} is a valid extension of @{term "s"} (@{text "vt_t"}): @{thm vt_t}.
 | 
|  |    422 |   \item Any thread created in @{term "t"} has priority no higher than @{term "prio"}, therefore
 | 
|  |    423 |     its precedence can not be higher than @{term "th"},  therefore
 | 
|  |    424 |     @{term "th"} remain to be the one with the highest precedence
 | 
|  |    425 |     (@{text "create_low"}):
 | 
|  |    426 |     @{thm [display] create_low}
 | 
|  |    427 |   \item Any adjustment of priority in 
 | 
|  |    428 |     @{term "t"} does not happen to @{term "th"} and 
 | 
|  |    429 |     the priority set is no higher than @{term "prio"}, therefore
 | 
|  |    430 |     @{term "th"} remain to be the one with the highest precedence (@{text "set_diff_low"}):
 | 
|  |    431 |     @{thm [display] set_diff_low}
 | 
|  |    432 |   \item Since we are investigating what happens to @{term "th"}, it is assumed 
 | 
|  |    433 |     @{term "th"} does not exit during @{term "t"} (@{text "exit_diff"}):
 | 
|  |    434 |     @{thm [display] exit_diff}
 | 
|  |    435 |   \end{enumerate}
 | 
|  |    436 | *}
 | 
|  |    437 | 
 | 
|  |    438 | text {* \noindent
 | 
|  |    439 |   All these assumptions are put into a predicate @{term "extend_highest_gen"}. 
 | 
|  |    440 |   It can be proved that @{term "extend_highest_gen"} holds 
 | 
|  |    441 |   for any moment @{text "i"} in it @{term "t"} (@{text "red_moment"}):
 | 
|  |    442 |   @{thm [display] red_moment}
 | 
|  |    443 |   
 | 
|  |    444 |   From this, an induction principle can be derived for @{text "t"}, so that 
 | 
|  |    445 |   properties already derived for @{term "t"} can be applied to any prefix 
 | 
|  |    446 |   of @{text "t"} in the proof of new properties 
 | 
|  |    447 |   about @{term "t"} (@{text "ind"}):
 | 
|  |    448 |   \begin{center}
 | 
|  |    449 |   @{thm[display] ind}
 | 
|  |    450 |   \end{center}
 | 
|  |    451 | 
 | 
|  |    452 |   The following properties can be proved about @{term "th"} in @{term "t"}:
 | 
|  |    453 |   \begin{enumerate}
 | 
|  |    454 |   \item In @{term "t"}, thread @{term "th"} is kept live and its 
 | 
|  |    455 |     precedence is preserved as well
 | 
|  |    456 |     (@{text "th_kept"}): 
 | 
|  |    457 |     @{thm [display] th_kept}
 | 
|  |    458 |   \item In @{term "t"}, thread @{term "th"}'s precedence is always the maximum among 
 | 
|  |    459 |     all living threads
 | 
|  |    460 |     (@{text "max_preced"}): 
 | 
|  |    461 |     @{thm [display] max_preced}
 | 
|  |    462 |   \item In @{term "t"}, thread @{term "th"}'s current precedence is always the maximum precedence
 | 
|  |    463 |     among all living threads
 | 
|  |    464 |     (@{text "th_cp_max_preced"}): 
 | 
|  |    465 |     @{thm [display] th_cp_max_preced}
 | 
|  |    466 |   \item In @{term "t"}, thread @{term "th"}'s current precedence is always the maximum current 
 | 
|  |    467 |     precedence among all living threads
 | 
|  |    468 |     (@{text "th_cp_max"}): 
 | 
|  |    469 |     @{thm [display] th_cp_max}
 | 
|  |    470 |   \item In @{term "t"}, thread @{term "th"}'s current precedence equals its precedence at moment 
 | 
|  |    471 |     @{term "s"}
 | 
|  |    472 |     (@{text "th_cp_preced"}): 
 | 
|  |    473 |     @{thm [display] th_cp_preced}
 | 
|  |    474 |   \end{enumerate}
 | 
|  |    475 |   *}
 | 
|  |    476 | 
 | 
|  |    477 | text {* \noindent
 | 
| 266 |    478 |   The main theorem of this part is to characterizing the running thread during @{term "t"} 
 | 
| 264 |    479 |   (@{text "runing_inversion_2"}):
 | 
|  |    480 |   @{thm [display] runing_inversion_2}
 | 
|  |    481 |   According to this, if a thread is running, it is either @{term "th"} or was
 | 
|  |    482 |   already live and held some resource 
 | 
|  |    483 |   at moment @{text "s"} (expressed by: @{text "cntV s th' < cntP s th'"}).
 | 
|  |    484 | 
 | 
|  |    485 |   Since there are only finite many threads live and holding some resource at any moment,
 | 
|  |    486 |   if every such thread can release all its resources in finite duration, then after finite
 | 
|  |    487 |   duration, none of them may block @{term "th"} anymore. So, no priority inversion may happen
 | 
|  |    488 |   then.
 | 
|  |    489 |   *}
 | 
|  |    490 | 
 | 
|  |    491 | (*<*)
 | 
|  |    492 | end
 | 
|  |    493 | (*>*)
 | 
|  |    494 | 
 | 
| 262 |    495 | section {* Properties to guide implementation \label{implement} *}
 | 
|  |    496 | 
 | 
| 264 |    497 | text {*
 | 
| 266 |    498 |   The properties (especially @{text "runing_inversion_2"}) convinced us that the model defined 
 | 
|  |    499 |   in Section \ref{model} does prevent indefinite priority inversion and therefore fulfills 
 | 
| 264 |    500 |   the fundamental requirement of Priority Inheritance protocol. Another purpose of this paper 
 | 
| 266 |    501 |   is to show how this model can be used to guide a concrete implementation. As discussed in
 | 
| 276 |    502 |   Section 5.6.5 of \cite{Vahalia96}, the implementation of Priority Inheritance in Solaris 
 | 
| 266 |    503 |   uses sophisticated linking data structure. Except discussing two scenarios to show how
 | 
|  |    504 |   the data structure should be manipulated, a lot of details of the implementation are missing. 
 | 
|  |    505 |   In \cite{Faria08,conf/fase/JahierHR09,WellingsBSB07} the protocol is described formally 
 | 
|  |    506 |   using different notations, but little information is given on how this protocol can be 
 | 
|  |    507 |   implemented efficiently, especially there is no information on how these data structure 
 | 
|  |    508 |   should be manipulated. 
 | 
|  |    509 | 
 | 
|  |    510 |   Because the scheduling of threads is based on current precedence, 
 | 
|  |    511 |   the central issue in implementation of Priority Inheritance is how to compute the precedence
 | 
|  |    512 |   correctly and efficiently. As long as the precedence is correct, it is very easy to 
 | 
|  |    513 |   modify the scheduling algorithm to select the correct thread to execute. 
 | 
|  |    514 | 
 | 
|  |    515 |   First, it can be proved that the computation of current precedence @{term "cp"} of a threads
 | 
|  |    516 |   only involves its children (@{text "cp_rec"}):
 | 
|  |    517 |   @{thm [display] cp_rec} 
 | 
|  |    518 |   where @{term "children s th"} represents the set of children of @{term "th"} in the current
 | 
|  |    519 |   RAG: 
 | 
|  |    520 |   \[
 | 
|  |    521 |   @{thm (lhs) children_def} @{text "\<equiv>"} @{thm (rhs) children_def}
 | 
|  |    522 |   \]
 | 
|  |    523 |   where the definition of @{term "child"} is: 
 | 
|  |    524 |   \[ @{thm (lhs) child_def} @{text "\<equiv>"}  @{thm (rhs) child_def}
 | 
|  |    525 |   \]
 | 
|  |    526 | 
 | 
|  |    527 |   The aim of this section is to fill the missing details of how current precedence should
 | 
|  |    528 |   be changed with the happening of events, with each event type treated by one subsection,
 | 
|  |    529 |   where the computation of @{term "cp"} uses lemma @{text "cp_rec"}.
 | 
|  |    530 |   *}
 | 
|  |    531 |  
 | 
|  |    532 | subsection {* Event @{text "Set th prio"} *}
 | 
|  |    533 | 
 | 
|  |    534 | (*<*)
 | 
|  |    535 | context step_set_cps
 | 
|  |    536 | begin
 | 
|  |    537 | (*>*)
 | 
|  |    538 | 
 | 
|  |    539 | text {*
 | 
|  |    540 |   The context under which event @{text "Set th prio"} happens is formalized as follows:
 | 
|  |    541 |   \begin{enumerate}
 | 
|  |    542 |     \item The formation of @{term "s"} (@{text "s_def"}): @{thm s_def}.
 | 
|  |    543 |     \item State @{term "s"} is a valid state (@{text "vt_s"}): @{thm vt_s}. This implies 
 | 
|  |    544 |       event @{text "Set th prio"} is eligible to happen under state @{term "s'"} and
 | 
|  |    545 |       state @{term "s'"} is a valid state.
 | 
|  |    546 |   \end{enumerate}
 | 
| 264 |    547 |   *}
 | 
|  |    548 | 
 | 
| 266 |    549 | text {* \noindent
 | 
|  |    550 |   Under such a context, we investigated how the current precedence @{term "cp"} of 
 | 
|  |    551 |   threads change from state @{term "s'"} to @{term "s"} and obtained the following
 | 
|  |    552 |   conclusions:
 | 
|  |    553 |   \begin{enumerate}
 | 
|  |    554 |   %% \item The RAG does not change (@{text "eq_dep"}): @{thm "eq_dep"}.
 | 
|  |    555 |   \item All threads with no dependence relation with thread @{term "th"} have their
 | 
|  |    556 |     @{term "cp"}-value unchanged (@{text "eq_cp"}):
 | 
|  |    557 |     @{thm [display] eq_cp}
 | 
|  |    558 |     This lemma implies the @{term "cp"}-value of @{term "th"}
 | 
|  |    559 |     and those threads which have a dependence relation with @{term "th"} might need
 | 
|  |    560 |     to be recomputed. The way to do this is to start from @{term "th"} 
 | 
|  |    561 |     and follow the @{term "depend"}-chain to recompute the @{term "cp"}-value of every 
 | 
|  |    562 |     encountered thread using lemma @{text "cp_rec"}. 
 | 
|  |    563 |     Since the @{term "depend"}-relation is loop free, this procedure 
 | 
|  |    564 |     can always stop. The the following lemma shows this procedure actually could stop earlier.
 | 
|  |    565 |   \item The following two lemma shows, if a thread the re-computation of which
 | 
|  |    566 |     gives an unchanged @{term "cp"}-value, the procedure described above can stop. 
 | 
|  |    567 |     \begin{enumerate}
 | 
|  |    568 |       \item Lemma @{text "eq_up_self"} shows if the re-computation of
 | 
|  |    569 |         @{term "th"}'s @{term "cp"} gives the same result, the procedure can stop:
 | 
|  |    570 |         @{thm [display] eq_up_self}
 | 
|  |    571 |       \item Lemma @{text "eq_up"}) shows if the re-computation at intermediate threads
 | 
|  |    572 |         gives unchanged result, the procedure can stop:
 | 
|  |    573 |         @{thm [display] eq_up}
 | 
|  |    574 |   \end{enumerate}
 | 
|  |    575 |   \end{enumerate}
 | 
|  |    576 |   *}
 | 
|  |    577 | 
 | 
|  |    578 | (*<*)
 | 
|  |    579 | end
 | 
|  |    580 | (*>*)
 | 
| 264 |    581 | 
 | 
| 272 |    582 | subsection {* Event @{text "V th cs"} *}
 | 
|  |    583 | 
 | 
|  |    584 | (*<*)
 | 
|  |    585 | context step_v_cps_nt
 | 
|  |    586 | begin
 | 
|  |    587 | (*>*)
 | 
|  |    588 | 
 | 
|  |    589 | text {*
 | 
|  |    590 |   The context under which event @{text "V th cs"} happens is formalized as follows:
 | 
|  |    591 |   \begin{enumerate}
 | 
|  |    592 |     \item The formation of @{term "s"} (@{text "s_def"}): @{thm s_def}.
 | 
|  |    593 |     \item State @{term "s"} is a valid state (@{text "vt_s"}): @{thm vt_s}. This implies 
 | 
|  |    594 |       event @{text "V th cs"} is eligible to happen under state @{term "s'"} and
 | 
|  |    595 |       state @{term "s'"} is a valid state.
 | 
|  |    596 |   \end{enumerate}
 | 
|  |    597 |   *}
 | 
|  |    598 | 
 | 
|  |    599 | text {* \noindent
 | 
|  |    600 |   Under such a context, we investigated how the current precedence @{term "cp"} of 
 | 
|  |    601 |   threads change from state @{term "s'"} to @{term "s"}. 
 | 
|  |    602 | 
 | 
|  |    603 | 
 | 
|  |    604 |   Two subcases are considerted, 
 | 
|  |    605 |   where the first is that there exits @{term "th'"} 
 | 
|  |    606 |   such that 
 | 
|  |    607 |   @{thm [display] nt} 
 | 
|  |    608 |   holds, which means there exists a thread @{term "th'"} to take over
 | 
|  |    609 |   the resource release by thread @{term "th"}. 
 | 
|  |    610 |   In this sub-case, the following results are obtained:
 | 
|  |    611 |   \begin{enumerate}
 | 
|  |    612 |   \item The change of RAG is given by lemma @{text "depend_s"}: 
 | 
|  |    613 |   @{thm [display] "depend_s"}
 | 
|  |    614 |   which shows two edges are removed while one is added. These changes imply how
 | 
|  |    615 |   the current precedences should be re-computed.
 | 
|  |    616 |   \item First all threads different from @{term "th"} and @{term "th'"} have their
 | 
|  |    617 |   @{term "cp"}-value kept, therefore do not need a re-computation
 | 
|  |    618 |   (@{text "cp_kept"}): @{thm [display] cp_kept}
 | 
|  |    619 |   This lemma also implies, only the @{term "cp"}-values of @{term "th"} and @{term "th'"}
 | 
|  |    620 |   need to be recomputed.
 | 
|  |    621 |   \end{enumerate}
 | 
|  |    622 |   *}
 | 
|  |    623 | 
 | 
|  |    624 | (*<*)
 | 
|  |    625 | end
 | 
|  |    626 | 
 | 
|  |    627 | context step_v_cps_nnt
 | 
|  |    628 | begin
 | 
|  |    629 | (*>*)
 | 
|  |    630 | 
 | 
|  |    631 | text {*
 | 
|  |    632 |   The other sub-case is when for all @{text "th'"}
 | 
|  |    633 |   @{thm [display] nnt}
 | 
|  |    634 |   holds, no such thread exists. The following results can be obtained for this 
 | 
|  |    635 |   sub-case:
 | 
|  |    636 |   \begin{enumerate}
 | 
|  |    637 |   \item The change of RAG is given by lemma @{text "depend_s"}:
 | 
|  |    638 |   @{thm [display] depend_s}
 | 
|  |    639 |   which means only one edge is removed.
 | 
|  |    640 |   \item In this case, no re-computation is needed (@{text "eq_cp"}):
 | 
|  |    641 |   @{thm [display] eq_cp}
 | 
|  |    642 |   \end{enumerate}
 | 
|  |    643 |   *}
 | 
|  |    644 | 
 | 
|  |    645 | (*<*)
 | 
|  |    646 | end
 | 
|  |    647 | (*>*)
 | 
|  |    648 | 
 | 
|  |    649 | 
 | 
|  |    650 | subsection {* Event @{text "P th cs"} *}
 | 
|  |    651 | 
 | 
|  |    652 | (*<*)
 | 
|  |    653 | context step_P_cps_e
 | 
|  |    654 | begin
 | 
|  |    655 | (*>*)
 | 
|  |    656 | 
 | 
|  |    657 | text {*
 | 
|  |    658 |   The context under which event @{text "P th cs"} happens is formalized as follows:
 | 
|  |    659 |   \begin{enumerate}
 | 
|  |    660 |     \item The formation of @{term "s"} (@{text "s_def"}): @{thm s_def}.
 | 
|  |    661 |     \item State @{term "s"} is a valid state (@{text "vt_s"}): @{thm vt_s}. This implies 
 | 
|  |    662 |       event @{text "P th cs"} is eligible to happen under state @{term "s'"} and
 | 
|  |    663 |       state @{term "s'"} is a valid state.
 | 
|  |    664 |   \end{enumerate}
 | 
|  |    665 | 
 | 
|  |    666 |   This case is further divided into two sub-cases. The first is when @{thm ee} holds.
 | 
|  |    667 |   The following results can be obtained:
 | 
|  |    668 |   \begin{enumerate}
 | 
|  |    669 |   \item One edge is added to the RAG (@{text "depend_s"}):
 | 
|  |    670 |     @{thm [display] depend_s}
 | 
|  |    671 |   \item No re-computation is needed (@{text "eq_cp"}):
 | 
|  |    672 |     @{thm [display] eq_cp}
 | 
|  |    673 |   \end{enumerate}
 | 
|  |    674 | *}
 | 
|  |    675 | 
 | 
|  |    676 | (*<*)
 | 
|  |    677 | end
 | 
|  |    678 | 
 | 
|  |    679 | context step_P_cps_ne
 | 
|  |    680 | begin
 | 
|  |    681 | (*>*)
 | 
|  |    682 | 
 | 
|  |    683 | text {*
 | 
|  |    684 |   The second is when @{thm ne} holds.
 | 
|  |    685 |   The following results can be obtained:
 | 
|  |    686 |   \begin{enumerate}
 | 
|  |    687 |   \item One edge is added to the RAG (@{text "depend_s"}):
 | 
|  |    688 |     @{thm [display] depend_s}
 | 
|  |    689 |   \item Threads with no dependence relation with @{term "th"} do not need a re-computation
 | 
|  |    690 |     of their @{term "cp"}-values (@{text "eq_cp"}):
 | 
|  |    691 |     @{thm [display] eq_cp}
 | 
|  |    692 |     This lemma implies all threads with a dependence relation with @{term "th"} may need 
 | 
|  |    693 |     re-computation.
 | 
|  |    694 |   \item Similar to the case of @{term "Set"}, the computation procedure could stop earlier
 | 
|  |    695 |     (@{text "eq_up"}):
 | 
|  |    696 |     @{thm [display] eq_up}
 | 
|  |    697 |   \end{enumerate}
 | 
|  |    698 | 
 | 
|  |    699 |   *}
 | 
|  |    700 | 
 | 
|  |    701 | (*<*)
 | 
|  |    702 | end
 | 
|  |    703 | (*>*)
 | 
|  |    704 | 
 | 
|  |    705 | subsection {* Event @{text "Create th prio"} *}
 | 
|  |    706 | 
 | 
|  |    707 | (*<*)
 | 
|  |    708 | context step_create_cps
 | 
|  |    709 | begin
 | 
|  |    710 | (*>*)
 | 
|  |    711 | 
 | 
|  |    712 | text {*
 | 
|  |    713 |   The context under which event @{text "Create th prio"} happens is formalized as follows:
 | 
|  |    714 |   \begin{enumerate}
 | 
|  |    715 |     \item The formation of @{term "s"} (@{text "s_def"}): @{thm s_def}.
 | 
|  |    716 |     \item State @{term "s"} is a valid state (@{text "vt_s"}): @{thm vt_s}. This implies 
 | 
|  |    717 |       event @{text "Create th prio"} is eligible to happen under state @{term "s'"} and
 | 
|  |    718 |       state @{term "s'"} is a valid state.
 | 
|  |    719 |   \end{enumerate}
 | 
|  |    720 |   The following results can be obtained under this context:
 | 
|  |    721 |   \begin{enumerate}
 | 
|  |    722 |   \item The RAG does not change (@{text "eq_dep"}):
 | 
|  |    723 |     @{thm [display] eq_dep}
 | 
|  |    724 |   \item All threads other than @{term "th"} do not need re-computation (@{text "eq_cp"}):
 | 
|  |    725 |     @{thm [display] eq_cp}
 | 
|  |    726 |   \item The @{term "cp"}-value of @{term "th"} equals its precedence 
 | 
|  |    727 |     (@{text "eq_cp_th"}):
 | 
|  |    728 |     @{thm [display] eq_cp_th}
 | 
|  |    729 |   \end{enumerate}
 | 
|  |    730 | 
 | 
|  |    731 | *}
 | 
|  |    732 | 
 | 
|  |    733 | 
 | 
|  |    734 | (*<*)
 | 
|  |    735 | end
 | 
|  |    736 | (*>*)
 | 
|  |    737 | 
 | 
|  |    738 | subsection {* Event @{text "Exit th"} *}
 | 
|  |    739 | 
 | 
|  |    740 | (*<*)
 | 
|  |    741 | context step_exit_cps
 | 
|  |    742 | begin
 | 
|  |    743 | (*>*)
 | 
|  |    744 | 
 | 
|  |    745 | text {*
 | 
|  |    746 |   The context under which event @{text "Exit th"} happens is formalized as follows:
 | 
|  |    747 |   \begin{enumerate}
 | 
|  |    748 |     \item The formation of @{term "s"} (@{text "s_def"}): @{thm s_def}.
 | 
|  |    749 |     \item State @{term "s"} is a valid state (@{text "vt_s"}): @{thm vt_s}. This implies 
 | 
|  |    750 |       event @{text "Exit th"} is eligible to happen under state @{term "s'"} and
 | 
|  |    751 |       state @{term "s'"} is a valid state.
 | 
|  |    752 |   \end{enumerate}
 | 
|  |    753 |   The following results can be obtained under this context:
 | 
|  |    754 |   \begin{enumerate}
 | 
|  |    755 |   \item The RAG does not change (@{text "eq_dep"}):
 | 
|  |    756 |     @{thm [display] eq_dep}
 | 
|  |    757 |   \item All threads other than @{term "th"} do not need re-computation (@{text "eq_cp"}):
 | 
|  |    758 |     @{thm [display] eq_cp}
 | 
|  |    759 |   \end{enumerate}
 | 
|  |    760 |   Since @{term th} does not live in state @{term "s"}, there is no need to compute 
 | 
|  |    761 |   its @{term cp}-value.
 | 
|  |    762 | *}
 | 
|  |    763 | 
 | 
|  |    764 | (*<*)
 | 
|  |    765 | end
 | 
|  |    766 | (*>*)
 | 
|  |    767 | 
 | 
|  |    768 | 
 | 
| 262 |    769 | section {* Related works \label{related} *}
 | 
|  |    770 | 
 | 
|  |    771 | text {*
 | 
|  |    772 |   \begin{enumerate}
 | 
|  |    773 |   \item {\em Integrating Priority Inheritance Algorithms in the Real-Time Specification for Java}
 | 
|  |    774 |     \cite{WellingsBSB07} models and verifies the combination of Priority Inheritance (PI) and 
 | 
|  |    775 |     Priority Ceiling Emulation (PCE) protocols in the setting of Java virtual machine 
 | 
|  |    776 |     using extended Timed Automata(TA) formalism of the UPPAAL tool. Although a detailed 
 | 
|  |    777 |     formal model of combined PI and PCE is given, the number of properties is quite 
 | 
|  |    778 |     small and the focus is put on the harmonious working of PI and PCE. Most key features of PI 
 | 
|  |    779 |     (as well as PCE) are not shown. Because of the limitation of the model checking technique
 | 
|  |    780 |     used there, properties are shown only for a small number of scenarios. Therefore, 
 | 
|  |    781 |     the verification does not show the correctness of the formal model itself in a 
 | 
|  |    782 |     convincing way.  
 | 
|  |    783 |   \item {\em Formal Development of Solutions for Real-Time Operating Systems with TLA+/TLC}
 | 
|  |    784 |     \cite{Faria08}. A formal model of PI is given in TLA+. Only 3 properties are shown 
 | 
|  |    785 |     for PI using model checking. The limitation of model checking is intrinsic to the work.
 | 
|  |    786 |   \item {\em Synchronous modeling and validation of priority inheritance schedulers}
 | 
|  |    787 |     \cite{conf/fase/JahierHR09}. Gives a formal model
 | 
|  |    788 |     of PI and PCE in AADL (Architecture Analysis \& Design Language) and checked 
 | 
|  |    789 |     several properties using model checking. The number of properties shown there is 
 | 
|  |    790 |     less than here and the scale is also limited by the model checking technique. 
 | 
|  |    791 |   \item {\em The Priority Ceiling Protocol: Formalization and Analysis Using PVS}
 | 
|  |    792 |     \cite{dutertre99b}. Formalized another protocol for Priority Inversion in the 
 | 
|  |    793 |     interactive theorem proving system PVS.
 | 
|  |    794 | \end{enumerate}
 | 
|  |    795 | 
 | 
|  |    796 | 
 | 
|  |    797 |   There are several works on inversion avoidance:
 | 
|  |    798 |   \begin{enumerate}
 | 
|  |    799 |   \item {\em Solving the group priority inversion problem in a timed asynchronous system}
 | 
|  |    800 |     \cite{Wang:2002:SGP}. The notion of Group Priority Inversion is introduced. The main 
 | 
|  |    801 |     strategy is still inversion avoidance. The method is by reordering requests 
 | 
|  |    802 |     in the setting of Client-Server.
 | 
|  |    803 |   \item {\em A Formalization of Priority Inversion} \cite{journals/rts/BabaogluMS93}. 
 | 
|  |    804 |     Formalized the notion of Priority 
 | 
|  |    805 |     Inversion and proposes methods to avoid it. 
 | 
|  |    806 |   \end{enumerate}
 | 
|  |    807 | 
 | 
|  |    808 |   {\em Examples of inaccurate specification of the protocol ???}.
 | 
|  |    809 | 
 | 
|  |    810 | *}
 | 
|  |    811 | 
 | 
|  |    812 | section {* Conclusions \label{conclusion} *}
 | 
|  |    813 | 
 | 
|  |    814 | (*<*)
 | 
|  |    815 | end
 | 
|  |    816 | (*>*) |