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(*<*)
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theory Paper
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imports CpsG ExtGG (* "~~/src/HOL/Library/LaTeXsugar" *) LaTeXsugar
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begin
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ML {*
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open Printer;
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show_question_marks_default := false;
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*}
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(*>*)
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section {* Introduction *}
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text {*
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Many real-time systems need to support processes with priorities and
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locking of resources. Locking of resources ensures mutual exclusion
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when accessing shared data or devices. Priorities allow scheduling
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of processes that need to finish their work within deadlines.
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Unfortunately, both features can interact in subtle ways leading to
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a problem, called \emph{Priority Inversion}. Suppose three processes
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having priorities $H$(igh), $M$(edium) and $L$(ow). We would expect
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that the process $H$ blocks any other process with lower priority
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and itself cannot be blocked by a process with lower priority. Alas,
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in a naive implementation of resource looking and priorities this
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property can be violated. Even worse, $H$ can be delayed
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indefinitely by processes with lower priorities. For this let $L$ be
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in the possession of a lock for a resource that also $H$ needs. $H$
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must therefore wait for $L$ to release this lock. The problem is
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that $L$ might in turn be blocked by any process with priority $M$,
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and so $H$ sits there potentially waiting indefinitely. Since $H$ is
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blocked by processes with lower priorities, the problem is called
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Priority Inversion. It was first described in
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\cite{Lampson:Redell:cacm:1980} in the context of the Mesa
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programming language designed for concurrent programming.
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If the problem of Priority Inversion is ignored, real-time systems
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can become unpredictable and resulting bugs can be hard to diagnose.
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The classic example where this happened is the software that
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controlled the Mars Pathfinder mission in 1997
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\cite{Reeves-Glenn-1998}. Once the spacecraft landed, the software
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shut down at irregular intervals leading to loss of project time, as
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normal operation of the craft could only resume the next day (the
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mission and data already collected were fortunately not lost, because
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of a clever system design). The reason for the shutdowns was that
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the scheduling software fell victim of Priority Inversion: a low
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priority task locking a resource prevented a high priority process
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from running in time leading to a system reset. Once the problem was found,
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it was rectified by enabling the Priority Inheritance Protocol in
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the scheduling software.
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The idea behind the \emph{Priority Inheritance Protocol} (PIP)
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\cite{journals/tc/ShaRL90} is to let the process $L$ temporarily
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inherit the high priority from $H$ until $L$ releases the locked
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resource. This solves the problem of $H$ having to wait
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indefinitely, because $L$ cannot, for example, be blocked by
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processes having priority $M$. While a few other solutions exist for the
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Priority Inversion problem \cite{Lampson:Redell:cacm:1980},
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PIP is one that is widely deployed and implemented, including in
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VxWorks (a proprietary real-time OS used in the Mars Pathfinder
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mission, in Boeing's 787 Dreamliner, Honda's ASIMO robot, etc.), but
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also as POSIX 1003.1c Standard, realised for example in libraries
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for FreeBSD, Solaris and Linux. One advantage of PIP is that
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increasing the priority of a process can be dynamically
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calculated. This is in contrast to, for example, \emph{Priority Ceiling}---another
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solution to the Priority Inversion problem, which however
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requires static analysis of the program in order to be helpful.
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However there has also been strong criticism against using PIP. For
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example it cannot prevent deathlocks and also blocking times can be
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substantial (more than just the duration of a critical section).
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However, most criticism of PIP centres around unreliabale
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implementations of PIP and PIP being complex. For example, Y...writes:
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\begin{quote}
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\it{}``Priority inheritance is neither efficient nor reliable. Implementations
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are either incomplete (and unreliable) or surprisingly complex and intrusive.''
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\end{quote}
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\noindent
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His solution is to avoid PIP altogether by not allowing critical sections to be
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pre-empted. While this might have been a sensible solution in 198..., in our
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modern multiprocessor world, this seems out of date.
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While there exists
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That there is a practical need
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Baker wrote on 13 July 2009 in the Linux Kernel mailing list:
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\begin{quote}
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\it{}``I observed in the kernel code
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(to my disgust), the Linux PIP implementation is a nightmare:
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extremely heavy weight, involving maintenance of a full wait-for
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graph, and requiring updates for a range of events, including
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priority changes and interruptions of wait operations.''
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\end{quote}
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\noindent
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This however means it is useful to look at PIP again from a more
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abstract level (but still concrete enough to inform an efficient implementation)
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and makes it an ideal candidate for a formal verification. One reason
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is of course that the original presentation of PIP, including a correcness ``proof'',
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is flawed. Y... points out a subletly that has been overlooked by Sha et al.
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But this is too simplistic. Consider
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Priority Inversion problem has been known since 1980
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\cite{Lampson:Redell:cacm:1980}, but Sha et al.~give the first
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thorough analysis and present an informal correctness proof for PIP
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.\footnote{Sha et al.~call it the
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\emph{Basic Priority Inheritance Protocol}.}
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POSIX.4: programming for the real world (Google eBook)
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However, there are further subtleties: just lowering the priority
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of the process $L$ to its low priority, as proposed in ???, is
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incorrect.\bigskip
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book: page 135, sec 5.6.5
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very little on implementations, not to mention implementations informed by
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formal correctness proofs.
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\noindent
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Priority inversion referrers to the phenomena where tasks with higher
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priority are blocked by ones with lower priority. If priority inversion
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is not controlled, there will be no guarantee the urgent tasks will be
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processed in time. As reported in \cite{Reeves-Glenn-1998},
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priority inversion used to cause software system resets and data lose in
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JPL's Mars pathfinder project. Therefore, the avoiding, detecting and controlling
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of priority inversion is a key issue to attain predictability in priority
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based real-time systems.
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The priority inversion phenomenon was first published in \cite{Lampson:Redell:cacm:1980}.
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The two protocols widely used to eliminate priority inversion, namely
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PI (Priority Inheritance) and PCE (Priority Ceiling Emulation), were proposed
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in \cite{journals/tc/ShaRL90}. PCE is less convenient to use because it requires
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static analysis of programs. Therefore, PI is more commonly used in
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practice\cite{locke-july02}. However, as pointed out in the literature,
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the analysis of priority inheritance protocol is quite subtle\cite{yodaiken-july02}.
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A formal analysis will certainly be helpful for us to understand and correctly
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implement PI. All existing formal analysis of PI
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\cite{conf/fase/JahierHR09,WellingsBSB07,Faria08} are based on the model checking
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technology. Because of the state explosion problem, model check
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is much like an exhaustive testing of finite models with limited size.
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The results obtained can not be safely generalized to models with arbitrarily
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large size. Worse still, since model checking is fully automatic, it give little
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insight on why the formal model is correct. It is therefore
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definitely desirable to analyze PI using theorem proving, which gives
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more general results as well as deeper insight. And this is the purpose
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of this paper which gives a formal analysis of PI in the interactive
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theorem prover Isabelle using Higher Order Logic (HOL). The formalization
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focuses on on two issues:
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\begin{enumerate}
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\item The correctness of the protocol model itself. A series of desirable properties is
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derived until we are fully convinced that the formal model of PI does
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eliminate priority inversion. And a better understanding of PI is so obtained
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in due course. For example, we find through formalization that the choice of
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next thread to take hold when a
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resource is released is irrelevant for the very basic property of PI to hold.
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A point never mentioned in literature.
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\item The correctness of the implementation. A series of properties is derived the meaning
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of which can be used as guidelines on how PI can be implemented efficiently and correctly.
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\end{enumerate}
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The rest of the paper is organized as follows: Section \ref{overview} gives an overview
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of PI. Section \ref{model} introduces the formal model of PI. Section \ref{general}
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discusses a series of basic properties of PI. Section \ref{extension} shows formally
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how priority inversion is controlled by PI. Section \ref{implement} gives properties
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which can be used for guidelines of implementation. Section \ref{related} discusses
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related works. Section \ref{conclusion} concludes the whole paper.
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The basic priority inheritance protocol has two problems:
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It does not prevent a deadlock from happening in a program with circular lock dependencies.
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A chain of blocking may be formed; blocking duration can be substantial, though bounded.
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Contributions
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Despite the wide use of Priority Inheritance Protocol in real time operating
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system, it's correctness has never been formally proved and mechanically checked.
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All existing verification are based on model checking technology. Full automatic
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verification gives little help to understand why the protocol is correct.
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And results such obtained only apply to models of limited size.
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This paper presents a formal verification based on theorem proving.
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Machine checked formal proof does help to get deeper understanding. We found
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the fact which is not mentioned in the literature, that the choice of next
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thread to take over when an critical resource is release does not affect the correctness
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of the protocol. The paper also shows how formal proof can help to construct
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correct and efficient implementation.\bigskip
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*}
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section {* An overview of priority inversion and priority inheritance \label{overview} *}
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text {*
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Priority inversion refers to the phenomenon when a thread with high priority is blocked
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by a thread with low priority. Priority happens when the high priority thread requests
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for some critical resource already taken by the low priority thread. Since the high
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priority thread has to wait for the low priority thread to complete, it is said to be
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blocked by the low priority thread. Priority inversion might prevent high priority
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thread from fulfill its task in time if the duration of priority inversion is indefinite
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and unpredictable. Indefinite priority inversion happens when indefinite number
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of threads with medium priorities is activated during the period when the high
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priority thread is blocked by the low priority thread. Although these medium
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priority threads can not preempt the high priority thread directly, they are able
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to preempt the low priority threads and cause it to stay in critical section for
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an indefinite long duration. In this way, the high priority thread may be blocked indefinitely.
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Priority inheritance is one protocol proposed to avoid indefinite priority inversion.
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The basic idea is to let the high priority thread donate its priority to the low priority
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thread holding the critical resource, so that it will not be preempted by medium priority
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threads. The thread with highest priority will not be blocked unless it is requesting
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some critical resource already taken by other threads. Viewed from a different angle,
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any thread which is able to block the highest priority threads must already hold some
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critical resource. Further more, it must have hold some critical resource at the
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moment the highest priority is created, otherwise, it may never get change to run and
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get hold. Since the number of such resource holding lower priority threads is finite,
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if every one of them finishes with its own critical section in a definite duration,
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the duration the highest priority thread is blocked is definite as well. The key to
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guarantee lower priority threads to finish in definite is to donate them the highest
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priority. In such cases, the lower priority threads is said to have inherited the
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highest priority. And this explains the name of the protocol:
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{\em Priority Inheritance} and how Priority Inheritance prevents indefinite delay.
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The objectives of this paper are:
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\begin{enumerate}
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\item Build the above mentioned idea into formal model and prove a series of properties
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until we are convinced that the formal model does fulfill the original idea.
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\item Show how formally derived properties can be used as guidelines for correct
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and efficient implementation.
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\end{enumerate}
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The proof is totally formal in the sense that every detail is reduced to the
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very first principles of Higher Order Logic. The nature of interactive theorem
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proving is for the human user to persuade computer program to accept its arguments.
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A clear and simple understanding of the problem at hand is both a prerequisite and a
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byproduct of such an effort, because everything has finally be reduced to the very
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first principle to be checked mechanically. The former intuitive explanation of
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Priority Inheritance is just such a byproduct.
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*}
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section {* Formal model of Priority Inheritance \label{model} *}
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text {*
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\input{../../generated/PrioGDef}
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*}
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section {* General properties of Priority Inheritance \label{general} *}
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text {*
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The following are several very basic prioprites:
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\begin{enumerate}
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\item All runing threads must be ready (@{text "runing_ready"}):
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@{thm[display] "runing_ready"}
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\item All ready threads must be living (@{text "readys_threads"}):
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@{thm[display] "readys_threads"}
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\item There are finite many living threads at any moment (@{text "finite_threads"}):
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@{thm[display] "finite_threads"}
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\item Every waiting queue does not contain duplcated elements (@{text "wq_distinct"}):
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@{thm[display] "wq_distinct"}
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\item All threads in waiting queues are living threads (@{text "wq_threads"}):
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@{thm[display] "wq_threads"}
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\item The event which can get a thread into waiting queue must be @{term "P"}-events
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(@{text "block_pre"}):
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@{thm[display] "block_pre"}
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\item A thread may never wait for two different critical resources
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(@{text "waiting_unique"}):
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@{thm[display] waiting_unique[of _ _ "cs\<^isub>1" "cs\<^isub>2"]}
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\item Every resource can only be held by one thread
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(@{text "held_unique"}):
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@{thm[display] held_unique[of _ "th\<^isub>1" _ "th\<^isub>2"]}
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\item Every living thread has an unique precedence
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(@{text "preced_unique"}):
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@{thm[display] preced_unique[of "th\<^isub>1" _ "th\<^isub>2"]}
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\end{enumerate}
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*}
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text {* \noindent
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The following lemmas show how RAG is changed with the execution of events:
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\begin{enumerate}
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\item Execution of @{term "Set"} does not change RAG (@{text "depend_set_unchanged"}):
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@{thm[display] depend_set_unchanged}
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\item Execution of @{term "Create"} does not change RAG (@{text "depend_create_unchanged"}):
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@{thm[display] depend_create_unchanged}
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\item Execution of @{term "Exit"} does not change RAG (@{text "depend_exit_unchanged"}):
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@{thm[display] depend_exit_unchanged}
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\item Execution of @{term "P"} (@{text "step_depend_p"}):
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@{thm[display] step_depend_p}
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\item Execution of @{term "V"} (@{text "step_depend_v"}):
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@{thm[display] step_depend_v}
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\end{enumerate}
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*}
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text {* \noindent
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These properties are used to derive the following important results about RAG:
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\begin{enumerate}
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\item RAG is loop free (@{text "acyclic_depend"}):
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@{thm [display] acyclic_depend}
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\item RAGs are finite (@{text "finite_depend"}):
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@{thm [display] finite_depend}
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\item Reverse paths in RAG are well founded (@{text "wf_dep_converse"}):
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@{thm [display] wf_dep_converse}
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\item The dependence relation represented by RAG has a tree structure (@{text "unique_depend"}):
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@{thm [display] unique_depend[of _ _ "n\<^isub>1" "n\<^isub>2"]}
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\item All threads in RAG are living threads
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(@{text "dm_depend_threads"} and @{text "range_in"}):
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@{thm [display] dm_depend_threads range_in}
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\end{enumerate}
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*}
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text {* \noindent
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The following lemmas show how every node in RAG can be chased to ready threads:
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\begin{enumerate}
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\item Every node in RAG can be chased to a ready thread (@{text "chain_building"}):
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@{thm [display] chain_building[rule_format]}
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\item The ready thread chased to is unique (@{text "dchain_unique"}):
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@{thm [display] dchain_unique[of _ _ "th\<^isub>1" "th\<^isub>2"]}
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\end{enumerate}
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*}
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text {* \noindent
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Properties about @{term "next_th"}:
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\begin{enumerate}
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\item The thread taking over is different from the thread which is releasing
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(@{text "next_th_neq"}):
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@{thm [display] next_th_neq}
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\item The thread taking over is unique
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(@{text "next_th_unique"}):
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@{thm [display] next_th_unique[of _ _ _ "th\<^isub>1" "th\<^isub>2"]}
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\end{enumerate}
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*}
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text {* \noindent
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Some deeper results about the system:
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\begin{enumerate}
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\item There can only be one running thread (@{text "runing_unique"}):
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@{thm [display] runing_unique[of _ "th\<^isub>1" "th\<^isub>2"]}
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\item The maximum of @{term "cp"} and @{term "preced"} are equal (@{text "max_cp_eq"}):
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@{thm [display] max_cp_eq}
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\item There must be one ready thread having the max @{term "cp"}-value
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(@{text "max_cp_readys_threads"}):
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@{thm [display] max_cp_readys_threads}
|
|
351 |
\end{enumerate}
|
|
352 |
*}
|
|
353 |
|
|
354 |
text {* \noindent
|
|
355 |
The relationship between the count of @{text "P"} and @{text "V"} and the number of
|
|
356 |
critical resources held by a thread is given as follows:
|
|
357 |
\begin{enumerate}
|
|
358 |
\item The @{term "V"}-operation decreases the number of critical resources
|
|
359 |
one thread holds (@{text "cntCS_v_dec"})
|
|
360 |
@{thm [display] cntCS_v_dec}
|
|
361 |
\item The number of @{text "V"} never exceeds the number of @{text "P"}
|
|
362 |
(@{text "cnp_cnv_cncs"}):
|
|
363 |
@{thm [display] cnp_cnv_cncs}
|
|
364 |
\item The number of @{text "V"} equals the number of @{text "P"} when
|
|
365 |
the relevant thread is not living:
|
|
366 |
(@{text "cnp_cnv_eq"}):
|
|
367 |
@{thm [display] cnp_cnv_eq}
|
|
368 |
\item When a thread is not living, it does not hold any critical resource
|
|
369 |
(@{text "not_thread_holdents"}):
|
|
370 |
@{thm [display] not_thread_holdents}
|
|
371 |
\item When the number of @{text "P"} equals the number of @{text "V"}, the relevant
|
|
372 |
thread does not hold any critical resource, therefore no thread can depend on it
|
|
373 |
(@{text "count_eq_dependents"}):
|
|
374 |
@{thm [display] count_eq_dependents}
|
|
375 |
\end{enumerate}
|
|
376 |
*}
|
262
|
377 |
|
|
378 |
section {* Key properties \label{extension} *}
|
|
379 |
|
264
|
380 |
(*<*)
|
|
381 |
context extend_highest_gen
|
|
382 |
begin
|
|
383 |
(*>*)
|
|
384 |
|
|
385 |
text {*
|
|
386 |
The essential of {\em Priority Inheritance} is to avoid indefinite priority inversion. For this
|
|
387 |
purpose, we need to investigate what happens after one thread takes the highest precedence.
|
|
388 |
A locale is used to describe such a situation, which assumes:
|
|
389 |
\begin{enumerate}
|
|
390 |
\item @{term "s"} is a valid state (@{text "vt_s"}):
|
|
391 |
@{thm vt_s}.
|
|
392 |
\item @{term "th"} is a living thread in @{term "s"} (@{text "threads_s"}):
|
|
393 |
@{thm threads_s}.
|
|
394 |
\item @{term "th"} has the highest precedence in @{term "s"} (@{text "highest"}):
|
|
395 |
@{thm highest}.
|
|
396 |
\item The precedence of @{term "th"} is @{term "Prc prio tm"} (@{text "preced_th"}):
|
|
397 |
@{thm preced_th}.
|
|
398 |
\end{enumerate}
|
|
399 |
*}
|
|
400 |
|
|
401 |
text {* \noindent
|
|
402 |
Under these assumptions, some basic priority can be derived for @{term "th"}:
|
|
403 |
\begin{enumerate}
|
|
404 |
\item The current precedence of @{term "th"} equals its own precedence (@{text "eq_cp_s_th"}):
|
|
405 |
@{thm [display] eq_cp_s_th}
|
|
406 |
\item The current precedence of @{term "th"} is the highest precedence in
|
|
407 |
the system (@{text "highest_cp_preced"}):
|
|
408 |
@{thm [display] highest_cp_preced}
|
|
409 |
\item The precedence of @{term "th"} is the highest precedence
|
|
410 |
in the system (@{text "highest_preced_thread"}):
|
|
411 |
@{thm [display] highest_preced_thread}
|
|
412 |
\item The current precedence of @{term "th"} is the highest current precedence
|
|
413 |
in the system (@{text "highest'"}):
|
|
414 |
@{thm [display] highest'}
|
|
415 |
\end{enumerate}
|
|
416 |
*}
|
|
417 |
|
|
418 |
text {* \noindent
|
|
419 |
To analysis what happens after state @{term "s"} a sub-locale is defined, which
|
|
420 |
assumes:
|
|
421 |
\begin{enumerate}
|
|
422 |
\item @{term "t"} is a valid extension of @{term "s"} (@{text "vt_t"}): @{thm vt_t}.
|
|
423 |
\item Any thread created in @{term "t"} has priority no higher than @{term "prio"}, therefore
|
|
424 |
its precedence can not be higher than @{term "th"}, therefore
|
|
425 |
@{term "th"} remain to be the one with the highest precedence
|
|
426 |
(@{text "create_low"}):
|
|
427 |
@{thm [display] create_low}
|
|
428 |
\item Any adjustment of priority in
|
|
429 |
@{term "t"} does not happen to @{term "th"} and
|
|
430 |
the priority set is no higher than @{term "prio"}, therefore
|
|
431 |
@{term "th"} remain to be the one with the highest precedence (@{text "set_diff_low"}):
|
|
432 |
@{thm [display] set_diff_low}
|
|
433 |
\item Since we are investigating what happens to @{term "th"}, it is assumed
|
|
434 |
@{term "th"} does not exit during @{term "t"} (@{text "exit_diff"}):
|
|
435 |
@{thm [display] exit_diff}
|
|
436 |
\end{enumerate}
|
|
437 |
*}
|
|
438 |
|
|
439 |
text {* \noindent
|
|
440 |
All these assumptions are put into a predicate @{term "extend_highest_gen"}.
|
|
441 |
It can be proved that @{term "extend_highest_gen"} holds
|
|
442 |
for any moment @{text "i"} in it @{term "t"} (@{text "red_moment"}):
|
|
443 |
@{thm [display] red_moment}
|
|
444 |
|
|
445 |
From this, an induction principle can be derived for @{text "t"}, so that
|
|
446 |
properties already derived for @{term "t"} can be applied to any prefix
|
|
447 |
of @{text "t"} in the proof of new properties
|
|
448 |
about @{term "t"} (@{text "ind"}):
|
|
449 |
\begin{center}
|
|
450 |
@{thm[display] ind}
|
|
451 |
\end{center}
|
|
452 |
|
|
453 |
The following properties can be proved about @{term "th"} in @{term "t"}:
|
|
454 |
\begin{enumerate}
|
|
455 |
\item In @{term "t"}, thread @{term "th"} is kept live and its
|
|
456 |
precedence is preserved as well
|
|
457 |
(@{text "th_kept"}):
|
|
458 |
@{thm [display] th_kept}
|
|
459 |
\item In @{term "t"}, thread @{term "th"}'s precedence is always the maximum among
|
|
460 |
all living threads
|
|
461 |
(@{text "max_preced"}):
|
|
462 |
@{thm [display] max_preced}
|
|
463 |
\item In @{term "t"}, thread @{term "th"}'s current precedence is always the maximum precedence
|
|
464 |
among all living threads
|
|
465 |
(@{text "th_cp_max_preced"}):
|
|
466 |
@{thm [display] th_cp_max_preced}
|
|
467 |
\item In @{term "t"}, thread @{term "th"}'s current precedence is always the maximum current
|
|
468 |
precedence among all living threads
|
|
469 |
(@{text "th_cp_max"}):
|
|
470 |
@{thm [display] th_cp_max}
|
|
471 |
\item In @{term "t"}, thread @{term "th"}'s current precedence equals its precedence at moment
|
|
472 |
@{term "s"}
|
|
473 |
(@{text "th_cp_preced"}):
|
|
474 |
@{thm [display] th_cp_preced}
|
|
475 |
\end{enumerate}
|
|
476 |
*}
|
|
477 |
|
|
478 |
text {* \noindent
|
266
|
479 |
The main theorem of this part is to characterizing the running thread during @{term "t"}
|
264
|
480 |
(@{text "runing_inversion_2"}):
|
|
481 |
@{thm [display] runing_inversion_2}
|
|
482 |
According to this, if a thread is running, it is either @{term "th"} or was
|
|
483 |
already live and held some resource
|
|
484 |
at moment @{text "s"} (expressed by: @{text "cntV s th' < cntP s th'"}).
|
|
485 |
|
|
486 |
Since there are only finite many threads live and holding some resource at any moment,
|
|
487 |
if every such thread can release all its resources in finite duration, then after finite
|
|
488 |
duration, none of them may block @{term "th"} anymore. So, no priority inversion may happen
|
|
489 |
then.
|
|
490 |
*}
|
|
491 |
|
|
492 |
(*<*)
|
|
493 |
end
|
|
494 |
(*>*)
|
|
495 |
|
262
|
496 |
section {* Properties to guide implementation \label{implement} *}
|
|
497 |
|
264
|
498 |
text {*
|
266
|
499 |
The properties (especially @{text "runing_inversion_2"}) convinced us that the model defined
|
|
500 |
in Section \ref{model} does prevent indefinite priority inversion and therefore fulfills
|
264
|
501 |
the fundamental requirement of Priority Inheritance protocol. Another purpose of this paper
|
266
|
502 |
is to show how this model can be used to guide a concrete implementation. As discussed in
|
|
503 |
Section 5.6.5 of \cite{Vahalia:1996:UI}, the implementation of Priority Inheritance in Solaris
|
|
504 |
uses sophisticated linking data structure. Except discussing two scenarios to show how
|
|
505 |
the data structure should be manipulated, a lot of details of the implementation are missing.
|
|
506 |
In \cite{Faria08,conf/fase/JahierHR09,WellingsBSB07} the protocol is described formally
|
|
507 |
using different notations, but little information is given on how this protocol can be
|
|
508 |
implemented efficiently, especially there is no information on how these data structure
|
|
509 |
should be manipulated.
|
|
510 |
|
|
511 |
Because the scheduling of threads is based on current precedence,
|
|
512 |
the central issue in implementation of Priority Inheritance is how to compute the precedence
|
|
513 |
correctly and efficiently. As long as the precedence is correct, it is very easy to
|
|
514 |
modify the scheduling algorithm to select the correct thread to execute.
|
|
515 |
|
|
516 |
First, it can be proved that the computation of current precedence @{term "cp"} of a threads
|
|
517 |
only involves its children (@{text "cp_rec"}):
|
|
518 |
@{thm [display] cp_rec}
|
|
519 |
where @{term "children s th"} represents the set of children of @{term "th"} in the current
|
|
520 |
RAG:
|
|
521 |
\[
|
|
522 |
@{thm (lhs) children_def} @{text "\<equiv>"} @{thm (rhs) children_def}
|
|
523 |
\]
|
|
524 |
where the definition of @{term "child"} is:
|
|
525 |
\[ @{thm (lhs) child_def} @{text "\<equiv>"} @{thm (rhs) child_def}
|
|
526 |
\]
|
|
527 |
|
|
528 |
The aim of this section is to fill the missing details of how current precedence should
|
|
529 |
be changed with the happening of events, with each event type treated by one subsection,
|
|
530 |
where the computation of @{term "cp"} uses lemma @{text "cp_rec"}.
|
|
531 |
*}
|
|
532 |
|
|
533 |
subsection {* Event @{text "Set th prio"} *}
|
|
534 |
|
|
535 |
(*<*)
|
|
536 |
context step_set_cps
|
|
537 |
begin
|
|
538 |
(*>*)
|
|
539 |
|
|
540 |
text {*
|
|
541 |
The context under which event @{text "Set th prio"} happens is formalized as follows:
|
|
542 |
\begin{enumerate}
|
|
543 |
\item The formation of @{term "s"} (@{text "s_def"}): @{thm s_def}.
|
|
544 |
\item State @{term "s"} is a valid state (@{text "vt_s"}): @{thm vt_s}. This implies
|
|
545 |
event @{text "Set th prio"} is eligible to happen under state @{term "s'"} and
|
|
546 |
state @{term "s'"} is a valid state.
|
|
547 |
\end{enumerate}
|
264
|
548 |
*}
|
|
549 |
|
266
|
550 |
text {* \noindent
|
|
551 |
Under such a context, we investigated how the current precedence @{term "cp"} of
|
|
552 |
threads change from state @{term "s'"} to @{term "s"} and obtained the following
|
|
553 |
conclusions:
|
|
554 |
\begin{enumerate}
|
|
555 |
%% \item The RAG does not change (@{text "eq_dep"}): @{thm "eq_dep"}.
|
|
556 |
\item All threads with no dependence relation with thread @{term "th"} have their
|
|
557 |
@{term "cp"}-value unchanged (@{text "eq_cp"}):
|
|
558 |
@{thm [display] eq_cp}
|
|
559 |
This lemma implies the @{term "cp"}-value of @{term "th"}
|
|
560 |
and those threads which have a dependence relation with @{term "th"} might need
|
|
561 |
to be recomputed. The way to do this is to start from @{term "th"}
|
|
562 |
and follow the @{term "depend"}-chain to recompute the @{term "cp"}-value of every
|
|
563 |
encountered thread using lemma @{text "cp_rec"}.
|
|
564 |
Since the @{term "depend"}-relation is loop free, this procedure
|
|
565 |
can always stop. The the following lemma shows this procedure actually could stop earlier.
|
|
566 |
\item The following two lemma shows, if a thread the re-computation of which
|
|
567 |
gives an unchanged @{term "cp"}-value, the procedure described above can stop.
|
|
568 |
\begin{enumerate}
|
|
569 |
\item Lemma @{text "eq_up_self"} shows if the re-computation of
|
|
570 |
@{term "th"}'s @{term "cp"} gives the same result, the procedure can stop:
|
|
571 |
@{thm [display] eq_up_self}
|
|
572 |
\item Lemma @{text "eq_up"}) shows if the re-computation at intermediate threads
|
|
573 |
gives unchanged result, the procedure can stop:
|
|
574 |
@{thm [display] eq_up}
|
|
575 |
\end{enumerate}
|
|
576 |
\end{enumerate}
|
|
577 |
*}
|
|
578 |
|
|
579 |
(*<*)
|
|
580 |
end
|
|
581 |
(*>*)
|
264
|
582 |
|
272
|
583 |
subsection {* Event @{text "V th cs"} *}
|
|
584 |
|
|
585 |
(*<*)
|
|
586 |
context step_v_cps_nt
|
|
587 |
begin
|
|
588 |
(*>*)
|
|
589 |
|
|
590 |
text {*
|
|
591 |
The context under which event @{text "V th cs"} happens is formalized as follows:
|
|
592 |
\begin{enumerate}
|
|
593 |
\item The formation of @{term "s"} (@{text "s_def"}): @{thm s_def}.
|
|
594 |
\item State @{term "s"} is a valid state (@{text "vt_s"}): @{thm vt_s}. This implies
|
|
595 |
event @{text "V th cs"} is eligible to happen under state @{term "s'"} and
|
|
596 |
state @{term "s'"} is a valid state.
|
|
597 |
\end{enumerate}
|
|
598 |
*}
|
|
599 |
|
|
600 |
text {* \noindent
|
|
601 |
Under such a context, we investigated how the current precedence @{term "cp"} of
|
|
602 |
threads change from state @{term "s'"} to @{term "s"}.
|
|
603 |
|
|
604 |
|
|
605 |
Two subcases are considerted,
|
|
606 |
where the first is that there exits @{term "th'"}
|
|
607 |
such that
|
|
608 |
@{thm [display] nt}
|
|
609 |
holds, which means there exists a thread @{term "th'"} to take over
|
|
610 |
the resource release by thread @{term "th"}.
|
|
611 |
In this sub-case, the following results are obtained:
|
|
612 |
\begin{enumerate}
|
|
613 |
\item The change of RAG is given by lemma @{text "depend_s"}:
|
|
614 |
@{thm [display] "depend_s"}
|
|
615 |
which shows two edges are removed while one is added. These changes imply how
|
|
616 |
the current precedences should be re-computed.
|
|
617 |
\item First all threads different from @{term "th"} and @{term "th'"} have their
|
|
618 |
@{term "cp"}-value kept, therefore do not need a re-computation
|
|
619 |
(@{text "cp_kept"}): @{thm [display] cp_kept}
|
|
620 |
This lemma also implies, only the @{term "cp"}-values of @{term "th"} and @{term "th'"}
|
|
621 |
need to be recomputed.
|
|
622 |
\end{enumerate}
|
|
623 |
*}
|
|
624 |
|
|
625 |
(*<*)
|
|
626 |
end
|
|
627 |
|
|
628 |
context step_v_cps_nnt
|
|
629 |
begin
|
|
630 |
(*>*)
|
|
631 |
|
|
632 |
text {*
|
|
633 |
The other sub-case is when for all @{text "th'"}
|
|
634 |
@{thm [display] nnt}
|
|
635 |
holds, no such thread exists. The following results can be obtained for this
|
|
636 |
sub-case:
|
|
637 |
\begin{enumerate}
|
|
638 |
\item The change of RAG is given by lemma @{text "depend_s"}:
|
|
639 |
@{thm [display] depend_s}
|
|
640 |
which means only one edge is removed.
|
|
641 |
\item In this case, no re-computation is needed (@{text "eq_cp"}):
|
|
642 |
@{thm [display] eq_cp}
|
|
643 |
\end{enumerate}
|
|
644 |
*}
|
|
645 |
|
|
646 |
(*<*)
|
|
647 |
end
|
|
648 |
(*>*)
|
|
649 |
|
|
650 |
|
|
651 |
subsection {* Event @{text "P th cs"} *}
|
|
652 |
|
|
653 |
(*<*)
|
|
654 |
context step_P_cps_e
|
|
655 |
begin
|
|
656 |
(*>*)
|
|
657 |
|
|
658 |
text {*
|
|
659 |
The context under which event @{text "P th cs"} happens is formalized as follows:
|
|
660 |
\begin{enumerate}
|
|
661 |
\item The formation of @{term "s"} (@{text "s_def"}): @{thm s_def}.
|
|
662 |
\item State @{term "s"} is a valid state (@{text "vt_s"}): @{thm vt_s}. This implies
|
|
663 |
event @{text "P th cs"} is eligible to happen under state @{term "s'"} and
|
|
664 |
state @{term "s'"} is a valid state.
|
|
665 |
\end{enumerate}
|
|
666 |
|
|
667 |
This case is further divided into two sub-cases. The first is when @{thm ee} holds.
|
|
668 |
The following results can be obtained:
|
|
669 |
\begin{enumerate}
|
|
670 |
\item One edge is added to the RAG (@{text "depend_s"}):
|
|
671 |
@{thm [display] depend_s}
|
|
672 |
\item No re-computation is needed (@{text "eq_cp"}):
|
|
673 |
@{thm [display] eq_cp}
|
|
674 |
\end{enumerate}
|
|
675 |
*}
|
|
676 |
|
|
677 |
(*<*)
|
|
678 |
end
|
|
679 |
|
|
680 |
context step_P_cps_ne
|
|
681 |
begin
|
|
682 |
(*>*)
|
|
683 |
|
|
684 |
text {*
|
|
685 |
The second is when @{thm ne} holds.
|
|
686 |
The following results can be obtained:
|
|
687 |
\begin{enumerate}
|
|
688 |
\item One edge is added to the RAG (@{text "depend_s"}):
|
|
689 |
@{thm [display] depend_s}
|
|
690 |
\item Threads with no dependence relation with @{term "th"} do not need a re-computation
|
|
691 |
of their @{term "cp"}-values (@{text "eq_cp"}):
|
|
692 |
@{thm [display] eq_cp}
|
|
693 |
This lemma implies all threads with a dependence relation with @{term "th"} may need
|
|
694 |
re-computation.
|
|
695 |
\item Similar to the case of @{term "Set"}, the computation procedure could stop earlier
|
|
696 |
(@{text "eq_up"}):
|
|
697 |
@{thm [display] eq_up}
|
|
698 |
\end{enumerate}
|
|
699 |
|
|
700 |
*}
|
|
701 |
|
|
702 |
(*<*)
|
|
703 |
end
|
|
704 |
(*>*)
|
|
705 |
|
|
706 |
subsection {* Event @{text "Create th prio"} *}
|
|
707 |
|
|
708 |
(*<*)
|
|
709 |
context step_create_cps
|
|
710 |
begin
|
|
711 |
(*>*)
|
|
712 |
|
|
713 |
text {*
|
|
714 |
The context under which event @{text "Create th prio"} happens is formalized as follows:
|
|
715 |
\begin{enumerate}
|
|
716 |
\item The formation of @{term "s"} (@{text "s_def"}): @{thm s_def}.
|
|
717 |
\item State @{term "s"} is a valid state (@{text "vt_s"}): @{thm vt_s}. This implies
|
|
718 |
event @{text "Create th prio"} is eligible to happen under state @{term "s'"} and
|
|
719 |
state @{term "s'"} is a valid state.
|
|
720 |
\end{enumerate}
|
|
721 |
The following results can be obtained under this context:
|
|
722 |
\begin{enumerate}
|
|
723 |
\item The RAG does not change (@{text "eq_dep"}):
|
|
724 |
@{thm [display] eq_dep}
|
|
725 |
\item All threads other than @{term "th"} do not need re-computation (@{text "eq_cp"}):
|
|
726 |
@{thm [display] eq_cp}
|
|
727 |
\item The @{term "cp"}-value of @{term "th"} equals its precedence
|
|
728 |
(@{text "eq_cp_th"}):
|
|
729 |
@{thm [display] eq_cp_th}
|
|
730 |
\end{enumerate}
|
|
731 |
|
|
732 |
*}
|
|
733 |
|
|
734 |
|
|
735 |
(*<*)
|
|
736 |
end
|
|
737 |
(*>*)
|
|
738 |
|
|
739 |
subsection {* Event @{text "Exit th"} *}
|
|
740 |
|
|
741 |
(*<*)
|
|
742 |
context step_exit_cps
|
|
743 |
begin
|
|
744 |
(*>*)
|
|
745 |
|
|
746 |
text {*
|
|
747 |
The context under which event @{text "Exit th"} happens is formalized as follows:
|
|
748 |
\begin{enumerate}
|
|
749 |
\item The formation of @{term "s"} (@{text "s_def"}): @{thm s_def}.
|
|
750 |
\item State @{term "s"} is a valid state (@{text "vt_s"}): @{thm vt_s}. This implies
|
|
751 |
event @{text "Exit th"} is eligible to happen under state @{term "s'"} and
|
|
752 |
state @{term "s'"} is a valid state.
|
|
753 |
\end{enumerate}
|
|
754 |
The following results can be obtained under this context:
|
|
755 |
\begin{enumerate}
|
|
756 |
\item The RAG does not change (@{text "eq_dep"}):
|
|
757 |
@{thm [display] eq_dep}
|
|
758 |
\item All threads other than @{term "th"} do not need re-computation (@{text "eq_cp"}):
|
|
759 |
@{thm [display] eq_cp}
|
|
760 |
\end{enumerate}
|
|
761 |
Since @{term th} does not live in state @{term "s"}, there is no need to compute
|
|
762 |
its @{term cp}-value.
|
|
763 |
*}
|
|
764 |
|
|
765 |
(*<*)
|
|
766 |
end
|
|
767 |
(*>*)
|
|
768 |
|
|
769 |
|
262
|
770 |
section {* Related works \label{related} *}
|
|
771 |
|
|
772 |
text {*
|
|
773 |
\begin{enumerate}
|
|
774 |
\item {\em Integrating Priority Inheritance Algorithms in the Real-Time Specification for Java}
|
|
775 |
\cite{WellingsBSB07} models and verifies the combination of Priority Inheritance (PI) and
|
|
776 |
Priority Ceiling Emulation (PCE) protocols in the setting of Java virtual machine
|
|
777 |
using extended Timed Automata(TA) formalism of the UPPAAL tool. Although a detailed
|
|
778 |
formal model of combined PI and PCE is given, the number of properties is quite
|
|
779 |
small and the focus is put on the harmonious working of PI and PCE. Most key features of PI
|
|
780 |
(as well as PCE) are not shown. Because of the limitation of the model checking technique
|
|
781 |
used there, properties are shown only for a small number of scenarios. Therefore,
|
|
782 |
the verification does not show the correctness of the formal model itself in a
|
|
783 |
convincing way.
|
|
784 |
\item {\em Formal Development of Solutions for Real-Time Operating Systems with TLA+/TLC}
|
|
785 |
\cite{Faria08}. A formal model of PI is given in TLA+. Only 3 properties are shown
|
|
786 |
for PI using model checking. The limitation of model checking is intrinsic to the work.
|
|
787 |
\item {\em Synchronous modeling and validation of priority inheritance schedulers}
|
|
788 |
\cite{conf/fase/JahierHR09}. Gives a formal model
|
|
789 |
of PI and PCE in AADL (Architecture Analysis \& Design Language) and checked
|
|
790 |
several properties using model checking. The number of properties shown there is
|
|
791 |
less than here and the scale is also limited by the model checking technique.
|
|
792 |
\item {\em The Priority Ceiling Protocol: Formalization and Analysis Using PVS}
|
|
793 |
\cite{dutertre99b}. Formalized another protocol for Priority Inversion in the
|
|
794 |
interactive theorem proving system PVS.
|
|
795 |
\end{enumerate}
|
|
796 |
|
|
797 |
|
|
798 |
There are several works on inversion avoidance:
|
|
799 |
\begin{enumerate}
|
|
800 |
\item {\em Solving the group priority inversion problem in a timed asynchronous system}
|
|
801 |
\cite{Wang:2002:SGP}. The notion of Group Priority Inversion is introduced. The main
|
|
802 |
strategy is still inversion avoidance. The method is by reordering requests
|
|
803 |
in the setting of Client-Server.
|
|
804 |
\item {\em A Formalization of Priority Inversion} \cite{journals/rts/BabaogluMS93}.
|
|
805 |
Formalized the notion of Priority
|
|
806 |
Inversion and proposes methods to avoid it.
|
|
807 |
\end{enumerate}
|
|
808 |
|
|
809 |
{\em Examples of inaccurate specification of the protocol ???}.
|
|
810 |
|
|
811 |
*}
|
|
812 |
|
|
813 |
section {* Conclusions \label{conclusion} *}
|
|
814 |
|
|
815 |
(*<*)
|
|
816 |
end
|
|
817 |
(*>*) |