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(*<*)
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theory Paper
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imports CpsG ExtGG LaTeXsugar
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begin
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ML {*
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show_question_marks_default := false;
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*}
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(*>*)
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section {* Introduction *}
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text {*
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Many realtime systems need to support processes with priorities and
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locking of resources. Locking of resources ensures... Priorities
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are needed so that some processes can finish their work within ``hard''
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deadlines. Unfortunately both features interact in subtle ways
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leading to the problem, called Priority Inversion. Suppose three
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processes with priorities $H$(igh), $M$(edium) and $L$(ow). We would
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assume that process $H$ cannot be blocked by any process with lower
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priority. Unfortunately in a naive implementation, this can happen
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and $H$ even can be delayed indefinitely by processes with lower
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priorities. For this let $L$ be in the posession of lock for a
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research which also $H$ needs. $H$ must therefore wait for $L$ to
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release this lock. Unfortunately, $L$ can in turn be blocked by any
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process with priority $M$, and so $H$ sits there potentially waiting
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indefinitely.
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If this problem of inversion of priorities is left untreated,
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systems can become unpredictable and have dire consequences. The
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classic example where this happened in practice is the software on
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the Mars pathfinder project. This software shut down at irregulare
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intervals leading to loss of project time (the mission and data was
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fortunately not lost, because of clever system design). The problem
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was that a high priority process and could only be restarted the
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next day.
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Priority inversion referrers to the phenomena where tasks with higher
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priority are blocked by ones with lower priority. If priority inversion
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is not controlled, there will be no guarantee the urgent tasks will be
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processed in time. As reported in \cite{Reeves-Glenn-1998},
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priority inversion used to cause software system resets and data lose in
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JPL's Mars pathfinder project. Therefore, the avoiding, detecting and controlling
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of priority inversion is a key issue to attain predictability in priority
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based real-time systems.
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The priority inversion phenomenon was first published in \cite{Lampson:Redell:cacm:1980}.
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The two protocols widely used to eliminate priority inversion, namely
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PI (Priority Inheritance) and PCE (Priority Ceiling Emulation), were proposed
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in \cite{journals/tc/ShaRL90}. PCE is less convenient to use because it requires
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static analysis of programs. Therefore, PI is more commonly used in
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practice\cite{locke-july02}. However, as pointed out in the literature,
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the analysis of priority inheritance protocol is quite subtle\cite{yodaiken-july02}.
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A formal analysis will certainly be helpful for us to understand and correctly
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implement PI. All existing formal analysis of PI
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\cite{conf/fase/JahierHR09,WellingsBSB07,Faria08} are based on the model checking
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technology. Because of the state explosion problem, model check
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is much like an exhaustive testing of finite models with limited size.
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The results obtained can not be safely generalized to models with arbitrarily
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large size. Worse still, since model checking is fully automatic, it give little
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insight on why the formal model is correct. It is therefore
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definitely desirable to analyze PI using theorem proving, which gives
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more general results as well as deeper insight. And this is the purpose
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of this paper which gives a formal analysis of PI in the interactive
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theorem prover Isabelle using Higher Order Logic (HOL). The formalization
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focuses on on two issues:
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\begin{enumerate}
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\item The correctness of the protocol model itself. A series of desirable properties is
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derived until we are fully convinced that the formal model of PI does
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eliminate priority inversion. And a better understanding of PI is so obtained
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in due course. For example, we find through formalization that the choice of
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next thread to take hold when a
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resource is released is irrelevant for the very basic property of PI to hold.
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A point never mentioned in literature.
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\item The correctness of the implementation. A series of properties is derived the meaning
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of which can be used as guidelines on how PI can be implemented efficiently and correctly.
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\end{enumerate}
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The rest of the paper is organized as follows: Section \ref{overview} gives an overview
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of PI. Section \ref{model} introduces the formal model of PI. Section \ref{general}
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discusses a series of basic properties of PI. Section \ref{extension} shows formally
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how priority inversion is controlled by PI. Section \ref{implement} gives properties
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which can be used for guidelines of implementation. Section \ref{related} discusses
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related works. Section \ref{conclusion} concludes the whole paper.
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Contributions
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Despite the wide use of Priority Inheritance Protocol in real time operating
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system, it's correctness has never been formally proved and mechanically checked.
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All existing verification are based on model checking technology. Full automatic
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verification gives little help to understand why the protocol is correct.
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And results such obtained only apply to models of limited size.
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This paper presents a formal verification based on theorem proving.
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Machine checked formal proof does help to get deeper understanding. We found
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the fact which is not mentioned in the literature, that the choice of next
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thread to take over when an critical resource is release does not affect the correctness
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of the protocol. The paper also shows how formal proof can help to construct
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correct and efficient implementation.\bigskip
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*}
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section {* An overview of priority inversion and priority inheritance \label{overview} *}
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text {*
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Priority inversion refers to the phenomenon when a thread with high priority is blocked
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by a thread with low priority. Priority happens when the high priority thread requests
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for some critical resource already taken by the low priority thread. Since the high
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priority thread has to wait for the low priority thread to complete, it is said to be
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blocked by the low priority thread. Priority inversion might prevent high priority
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thread from fulfill its task in time if the duration of priority inversion is indefinite
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and unpredictable. Indefinite priority inversion happens when indefinite number
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of threads with medium priorities is activated during the period when the high
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priority thread is blocked by the low priority thread. Although these medium
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priority threads can not preempt the high priority thread directly, they are able
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to preempt the low priority threads and cause it to stay in critical section for
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an indefinite long duration. In this way, the high priority thread may be blocked indefinitely.
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Priority inheritance is one protocol proposed to avoid indefinite priority inversion.
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The basic idea is to let the high priority thread donate its priority to the low priority
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thread holding the critical resource, so that it will not be preempted by medium priority
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threads. The thread with highest priority will not be blocked unless it is requesting
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some critical resource already taken by other threads. Viewed from a different angle,
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any thread which is able to block the highest priority threads must already hold some
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critical resource. Further more, it must have hold some critical resource at the
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moment the highest priority is created, otherwise, it may never get change to run and
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get hold. Since the number of such resource holding lower priority threads is finite,
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if every one of them finishes with its own critical section in a definite duration,
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the duration the highest priority thread is blocked is definite as well. The key to
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guarantee lower priority threads to finish in definite is to donate them the highest
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priority. In such cases, the lower priority threads is said to have inherited the
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highest priority. And this explains the name of the protocol:
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{\em Priority Inheritance} and how Priority Inheritance prevents indefinite delay.
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The objectives of this paper are:
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\begin{enumerate}
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\item Build the above mentioned idea into formal model and prove a series of properties
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until we are convinced that the formal model does fulfill the original idea.
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\item Show how formally derived properties can be used as guidelines for correct
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and efficient implementation.
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\end{enumerate}
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The proof is totally formal in the sense that every detail is reduced to the
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very first principles of Higher Order Logic. The nature of interactive theorem
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proving is for the human user to persuade computer program to accept its arguments.
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A clear and simple understanding of the problem at hand is both a prerequisite and a
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byproduct of such an effort, because everything has finally be reduced to the very
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first principle to be checked mechanically. The former intuitive explanation of
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Priority Inheritance is just such a byproduct.
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*}
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section {* Formal model of Priority Inheritance \label{model} *}
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text {*
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\input{../../generated/PrioGDef}
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*}
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section {* General properties of Priority Inheritance \label{general} *}
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(*<*)
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ML {*
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(*val () = show_question_marks_default := false;*)
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*}
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(*>*)
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text {*
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The following are several very basic prioprites:
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\begin{enumerate}
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\item All runing threads must be ready (@{text "runing_ready"}):
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@{thm[display] "runing_ready"}
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\item All ready threads must be living (@{text "readys_threads"}):
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@{thm[display] "readys_threads"}
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\item There are finite many living threads at any moment (@{text "finite_threads"}):
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@{thm[display] "finite_threads"}
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\item Every waiting queue does not contain duplcated elements (@{text "wq_distinct"}):
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@{thm[display] "wq_distinct"}
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\item All threads in waiting queues are living threads (@{text "wq_threads"}):
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@{thm[display] "wq_threads"}
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\item The event which can get a thread into waiting queue must be @{term "P"}-events
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(@{text "block_pre"}):
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@{thm[display] "block_pre"}
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\item A thread may never wait for two different critical resources
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(@{text "waiting_unique"}):
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@{thm[display] waiting_unique[of _ _ "cs\<^isub>1" "cs\<^isub>2"]}
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\item Every resource can only be held by one thread
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(@{text "held_unique"}):
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@{thm[display] held_unique[of _ "th\<^isub>1" _ "th\<^isub>2"]}
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\item Every living thread has an unique precedence
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(@{text "preced_unique"}):
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@{thm[display] preced_unique[of "th\<^isub>1" _ "th\<^isub>2"]}
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\end{enumerate}
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*}
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text {* \noindent
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The following lemmas show how RAG is changed with the execution of events:
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\begin{enumerate}
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\item Execution of @{term "Set"} does not change RAG (@{text "depend_set_unchanged"}):
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@{thm[display] depend_set_unchanged}
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\item Execution of @{term "Create"} does not change RAG (@{text "depend_create_unchanged"}):
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@{thm[display] depend_create_unchanged}
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\item Execution of @{term "Exit"} does not change RAG (@{text "depend_exit_unchanged"}):
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@{thm[display] depend_exit_unchanged}
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\item Execution of @{term "P"} (@{text "step_depend_p"}):
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@{thm[display] step_depend_p}
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\item Execution of @{term "V"} (@{text "step_depend_v"}):
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@{thm[display] step_depend_v}
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\end{enumerate}
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*}
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text {* \noindent
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These properties are used to derive the following important results about RAG:
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\begin{enumerate}
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\item RAG is loop free (@{text "acyclic_depend"}):
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@{thm [display] acyclic_depend}
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\item RAGs are finite (@{text "finite_depend"}):
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@{thm [display] finite_depend}
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\item Reverse paths in RAG are well founded (@{text "wf_dep_converse"}):
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@{thm [display] wf_dep_converse}
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\item The dependence relation represented by RAG has a tree structure (@{text "unique_depend"}):
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@{thm [display] unique_depend[of _ _ "n\<^isub>1" "n\<^isub>2"]}
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\item All threads in RAG are living threads
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(@{text "dm_depend_threads"} and @{text "range_in"}):
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@{thm [display] dm_depend_threads range_in}
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\end{enumerate}
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*}
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text {* \noindent
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The following lemmas show how every node in RAG can be chased to ready threads:
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\begin{enumerate}
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\item Every node in RAG can be chased to a ready thread (@{text "chain_building"}):
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@{thm [display] chain_building[rule_format]}
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\item The ready thread chased to is unique (@{text "dchain_unique"}):
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@{thm [display] dchain_unique[of _ _ "th\<^isub>1" "th\<^isub>2"]}
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\end{enumerate}
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*}
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text {* \noindent
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Properties about @{term "next_th"}:
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\begin{enumerate}
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\item The thread taking over is different from the thread which is releasing
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(@{text "next_th_neq"}):
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@{thm [display] next_th_neq}
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\item The thread taking over is unique
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(@{text "next_th_unique"}):
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@{thm [display] next_th_unique[of _ _ _ "th\<^isub>1" "th\<^isub>2"]}
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\end{enumerate}
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*}
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text {* \noindent
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Some deeper results about the system:
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\begin{enumerate}
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\item There can only be one running thread (@{text "runing_unique"}):
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@{thm [display] runing_unique[of _ "th\<^isub>1" "th\<^isub>2"]}
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\item The maximum of @{term "cp"} and @{term "preced"} are equal (@{text "max_cp_eq"}):
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@{thm [display] max_cp_eq}
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\item There must be one ready thread having the max @{term "cp"}-value
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(@{text "max_cp_readys_threads"}):
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@{thm [display] max_cp_readys_threads}
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\end{enumerate}
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*}
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text {* \noindent
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The relationship between the count of @{text "P"} and @{text "V"} and the number of
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critical resources held by a thread is given as follows:
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\begin{enumerate}
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\item The @{term "V"}-operation decreases the number of critical resources
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one thread holds (@{text "cntCS_v_dec"})
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@{thm [display] cntCS_v_dec}
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\item The number of @{text "V"} never exceeds the number of @{text "P"}
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(@{text "cnp_cnv_cncs"}):
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@{thm [display] cnp_cnv_cncs}
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\item The number of @{text "V"} equals the number of @{text "P"} when
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the relevant thread is not living:
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(@{text "cnp_cnv_eq"}):
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@{thm [display] cnp_cnv_eq}
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\item When a thread is not living, it does not hold any critical resource
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(@{text "not_thread_holdents"}):
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@{thm [display] not_thread_holdents}
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\item When the number of @{text "P"} equals the number of @{text "V"}, the relevant
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thread does not hold any critical resource, therefore no thread can depend on it
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(@{text "count_eq_dependents"}):
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@{thm [display] count_eq_dependents}
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\end{enumerate}
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*}
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section {* Key properties \label{extension} *}
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(*<*)
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context extend_highest_gen
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begin
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(*>*)
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text {*
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The essential of {\em Priority Inheritance} is to avoid indefinite priority inversion. For this
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purpose, we need to investigate what happens after one thread takes the highest precedence.
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A locale is used to describe such a situation, which assumes:
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\begin{enumerate}
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\item @{term "s"} is a valid state (@{text "vt_s"}):
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@{thm vt_s}.
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\item @{term "th"} is a living thread in @{term "s"} (@{text "threads_s"}):
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@{thm threads_s}.
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\item @{term "th"} has the highest precedence in @{term "s"} (@{text "highest"}):
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@{thm highest}.
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\item The precedence of @{term "th"} is @{term "Prc prio tm"} (@{text "preced_th"}):
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@{thm preced_th}.
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\end{enumerate}
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*}
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text {* \noindent
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Under these assumptions, some basic priority can be derived for @{term "th"}:
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\begin{enumerate}
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\item The current precedence of @{term "th"} equals its own precedence (@{text "eq_cp_s_th"}):
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@{thm [display] eq_cp_s_th}
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\item The current precedence of @{term "th"} is the highest precedence in
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the system (@{text "highest_cp_preced"}):
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@{thm [display] highest_cp_preced}
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\item The precedence of @{term "th"} is the highest precedence
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in the system (@{text "highest_preced_thread"}):
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@{thm [display] highest_preced_thread}
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\item The current precedence of @{term "th"} is the highest current precedence
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in the system (@{text "highest'"}):
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@{thm [display] highest'}
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\end{enumerate}
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*}
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text {* \noindent
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To analysis what happens after state @{term "s"} a sub-locale is defined, which
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assumes:
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\begin{enumerate}
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\item @{term "t"} is a valid extension of @{term "s"} (@{text "vt_t"}): @{thm vt_t}.
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\item Any thread created in @{term "t"} has priority no higher than @{term "prio"}, therefore
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its precedence can not be higher than @{term "th"}, therefore
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@{term "th"} remain to be the one with the highest precedence
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(@{text "create_low"}):
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@{thm [display] create_low}
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\item Any adjustment of priority in
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@{term "t"} does not happen to @{term "th"} and
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the priority set is no higher than @{term "prio"}, therefore
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@{term "th"} remain to be the one with the highest precedence (@{text "set_diff_low"}):
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@{thm [display] set_diff_low}
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\item Since we are investigating what happens to @{term "th"}, it is assumed
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@{term "th"} does not exit during @{term "t"} (@{text "exit_diff"}):
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@{thm [display] exit_diff}
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\end{enumerate}
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*}
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text {* \noindent
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All these assumptions are put into a predicate @{term "extend_highest_gen"}.
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It can be proved that @{term "extend_highest_gen"} holds
|
|
349 |
for any moment @{text "i"} in it @{term "t"} (@{text "red_moment"}):
|
|
350 |
@{thm [display] red_moment}
|
|
351 |
|
|
352 |
From this, an induction principle can be derived for @{text "t"}, so that
|
|
353 |
properties already derived for @{term "t"} can be applied to any prefix
|
|
354 |
of @{text "t"} in the proof of new properties
|
|
355 |
about @{term "t"} (@{text "ind"}):
|
|
356 |
\begin{center}
|
|
357 |
@{thm[display] ind}
|
|
358 |
\end{center}
|
|
359 |
|
|
360 |
The following properties can be proved about @{term "th"} in @{term "t"}:
|
|
361 |
\begin{enumerate}
|
|
362 |
\item In @{term "t"}, thread @{term "th"} is kept live and its
|
|
363 |
precedence is preserved as well
|
|
364 |
(@{text "th_kept"}):
|
|
365 |
@{thm [display] th_kept}
|
|
366 |
\item In @{term "t"}, thread @{term "th"}'s precedence is always the maximum among
|
|
367 |
all living threads
|
|
368 |
(@{text "max_preced"}):
|
|
369 |
@{thm [display] max_preced}
|
|
370 |
\item In @{term "t"}, thread @{term "th"}'s current precedence is always the maximum precedence
|
|
371 |
among all living threads
|
|
372 |
(@{text "th_cp_max_preced"}):
|
|
373 |
@{thm [display] th_cp_max_preced}
|
|
374 |
\item In @{term "t"}, thread @{term "th"}'s current precedence is always the maximum current
|
|
375 |
precedence among all living threads
|
|
376 |
(@{text "th_cp_max"}):
|
|
377 |
@{thm [display] th_cp_max}
|
|
378 |
\item In @{term "t"}, thread @{term "th"}'s current precedence equals its precedence at moment
|
|
379 |
@{term "s"}
|
|
380 |
(@{text "th_cp_preced"}):
|
|
381 |
@{thm [display] th_cp_preced}
|
|
382 |
\end{enumerate}
|
|
383 |
*}
|
|
384 |
|
|
385 |
text {* \noindent
|
266
|
386 |
The main theorem of this part is to characterizing the running thread during @{term "t"}
|
264
|
387 |
(@{text "runing_inversion_2"}):
|
|
388 |
@{thm [display] runing_inversion_2}
|
|
389 |
According to this, if a thread is running, it is either @{term "th"} or was
|
|
390 |
already live and held some resource
|
|
391 |
at moment @{text "s"} (expressed by: @{text "cntV s th' < cntP s th'"}).
|
|
392 |
|
|
393 |
Since there are only finite many threads live and holding some resource at any moment,
|
|
394 |
if every such thread can release all its resources in finite duration, then after finite
|
|
395 |
duration, none of them may block @{term "th"} anymore. So, no priority inversion may happen
|
|
396 |
then.
|
|
397 |
*}
|
|
398 |
|
|
399 |
(*<*)
|
|
400 |
end
|
|
401 |
(*>*)
|
|
402 |
|
262
|
403 |
section {* Properties to guide implementation \label{implement} *}
|
|
404 |
|
264
|
405 |
text {*
|
266
|
406 |
The properties (especially @{text "runing_inversion_2"}) convinced us that the model defined
|
|
407 |
in Section \ref{model} does prevent indefinite priority inversion and therefore fulfills
|
264
|
408 |
the fundamental requirement of Priority Inheritance protocol. Another purpose of this paper
|
266
|
409 |
is to show how this model can be used to guide a concrete implementation. As discussed in
|
|
410 |
Section 5.6.5 of \cite{Vahalia:1996:UI}, the implementation of Priority Inheritance in Solaris
|
|
411 |
uses sophisticated linking data structure. Except discussing two scenarios to show how
|
|
412 |
the data structure should be manipulated, a lot of details of the implementation are missing.
|
|
413 |
In \cite{Faria08,conf/fase/JahierHR09,WellingsBSB07} the protocol is described formally
|
|
414 |
using different notations, but little information is given on how this protocol can be
|
|
415 |
implemented efficiently, especially there is no information on how these data structure
|
|
416 |
should be manipulated.
|
|
417 |
|
|
418 |
Because the scheduling of threads is based on current precedence,
|
|
419 |
the central issue in implementation of Priority Inheritance is how to compute the precedence
|
|
420 |
correctly and efficiently. As long as the precedence is correct, it is very easy to
|
|
421 |
modify the scheduling algorithm to select the correct thread to execute.
|
|
422 |
|
|
423 |
First, it can be proved that the computation of current precedence @{term "cp"} of a threads
|
|
424 |
only involves its children (@{text "cp_rec"}):
|
|
425 |
@{thm [display] cp_rec}
|
|
426 |
where @{term "children s th"} represents the set of children of @{term "th"} in the current
|
|
427 |
RAG:
|
|
428 |
\[
|
|
429 |
@{thm (lhs) children_def} @{text "\<equiv>"} @{thm (rhs) children_def}
|
|
430 |
\]
|
|
431 |
where the definition of @{term "child"} is:
|
|
432 |
\[ @{thm (lhs) child_def} @{text "\<equiv>"} @{thm (rhs) child_def}
|
|
433 |
\]
|
|
434 |
|
|
435 |
The aim of this section is to fill the missing details of how current precedence should
|
|
436 |
be changed with the happening of events, with each event type treated by one subsection,
|
|
437 |
where the computation of @{term "cp"} uses lemma @{text "cp_rec"}.
|
|
438 |
*}
|
|
439 |
|
|
440 |
subsection {* Event @{text "Set th prio"} *}
|
|
441 |
|
|
442 |
(*<*)
|
|
443 |
context step_set_cps
|
|
444 |
begin
|
|
445 |
(*>*)
|
|
446 |
|
|
447 |
text {*
|
|
448 |
The context under which event @{text "Set th prio"} happens is formalized as follows:
|
|
449 |
\begin{enumerate}
|
|
450 |
\item The formation of @{term "s"} (@{text "s_def"}): @{thm s_def}.
|
|
451 |
\item State @{term "s"} is a valid state (@{text "vt_s"}): @{thm vt_s}. This implies
|
|
452 |
event @{text "Set th prio"} is eligible to happen under state @{term "s'"} and
|
|
453 |
state @{term "s'"} is a valid state.
|
|
454 |
\end{enumerate}
|
264
|
455 |
*}
|
|
456 |
|
266
|
457 |
text {* \noindent
|
|
458 |
Under such a context, we investigated how the current precedence @{term "cp"} of
|
|
459 |
threads change from state @{term "s'"} to @{term "s"} and obtained the following
|
|
460 |
conclusions:
|
|
461 |
\begin{enumerate}
|
|
462 |
%% \item The RAG does not change (@{text "eq_dep"}): @{thm "eq_dep"}.
|
|
463 |
\item All threads with no dependence relation with thread @{term "th"} have their
|
|
464 |
@{term "cp"}-value unchanged (@{text "eq_cp"}):
|
|
465 |
@{thm [display] eq_cp}
|
|
466 |
This lemma implies the @{term "cp"}-value of @{term "th"}
|
|
467 |
and those threads which have a dependence relation with @{term "th"} might need
|
|
468 |
to be recomputed. The way to do this is to start from @{term "th"}
|
|
469 |
and follow the @{term "depend"}-chain to recompute the @{term "cp"}-value of every
|
|
470 |
encountered thread using lemma @{text "cp_rec"}.
|
|
471 |
Since the @{term "depend"}-relation is loop free, this procedure
|
|
472 |
can always stop. The the following lemma shows this procedure actually could stop earlier.
|
|
473 |
\item The following two lemma shows, if a thread the re-computation of which
|
|
474 |
gives an unchanged @{term "cp"}-value, the procedure described above can stop.
|
|
475 |
\begin{enumerate}
|
|
476 |
\item Lemma @{text "eq_up_self"} shows if the re-computation of
|
|
477 |
@{term "th"}'s @{term "cp"} gives the same result, the procedure can stop:
|
|
478 |
@{thm [display] eq_up_self}
|
|
479 |
\item Lemma @{text "eq_up"}) shows if the re-computation at intermediate threads
|
|
480 |
gives unchanged result, the procedure can stop:
|
|
481 |
@{thm [display] eq_up}
|
|
482 |
\end{enumerate}
|
|
483 |
\end{enumerate}
|
|
484 |
*}
|
|
485 |
|
|
486 |
(*<*)
|
|
487 |
end
|
|
488 |
(*>*)
|
264
|
489 |
|
262
|
490 |
section {* Related works \label{related} *}
|
|
491 |
|
|
492 |
text {*
|
|
493 |
\begin{enumerate}
|
|
494 |
\item {\em Integrating Priority Inheritance Algorithms in the Real-Time Specification for Java}
|
|
495 |
\cite{WellingsBSB07} models and verifies the combination of Priority Inheritance (PI) and
|
|
496 |
Priority Ceiling Emulation (PCE) protocols in the setting of Java virtual machine
|
|
497 |
using extended Timed Automata(TA) formalism of the UPPAAL tool. Although a detailed
|
|
498 |
formal model of combined PI and PCE is given, the number of properties is quite
|
|
499 |
small and the focus is put on the harmonious working of PI and PCE. Most key features of PI
|
|
500 |
(as well as PCE) are not shown. Because of the limitation of the model checking technique
|
|
501 |
used there, properties are shown only for a small number of scenarios. Therefore,
|
|
502 |
the verification does not show the correctness of the formal model itself in a
|
|
503 |
convincing way.
|
|
504 |
\item {\em Formal Development of Solutions for Real-Time Operating Systems with TLA+/TLC}
|
|
505 |
\cite{Faria08}. A formal model of PI is given in TLA+. Only 3 properties are shown
|
|
506 |
for PI using model checking. The limitation of model checking is intrinsic to the work.
|
|
507 |
\item {\em Synchronous modeling and validation of priority inheritance schedulers}
|
|
508 |
\cite{conf/fase/JahierHR09}. Gives a formal model
|
|
509 |
of PI and PCE in AADL (Architecture Analysis \& Design Language) and checked
|
|
510 |
several properties using model checking. The number of properties shown there is
|
|
511 |
less than here and the scale is also limited by the model checking technique.
|
|
512 |
\item {\em The Priority Ceiling Protocol: Formalization and Analysis Using PVS}
|
|
513 |
\cite{dutertre99b}. Formalized another protocol for Priority Inversion in the
|
|
514 |
interactive theorem proving system PVS.
|
|
515 |
\end{enumerate}
|
|
516 |
|
|
517 |
|
|
518 |
There are several works on inversion avoidance:
|
|
519 |
\begin{enumerate}
|
|
520 |
\item {\em Solving the group priority inversion problem in a timed asynchronous system}
|
|
521 |
\cite{Wang:2002:SGP}. The notion of Group Priority Inversion is introduced. The main
|
|
522 |
strategy is still inversion avoidance. The method is by reordering requests
|
|
523 |
in the setting of Client-Server.
|
|
524 |
\item {\em A Formalization of Priority Inversion} \cite{journals/rts/BabaogluMS93}.
|
|
525 |
Formalized the notion of Priority
|
|
526 |
Inversion and proposes methods to avoid it.
|
|
527 |
\end{enumerate}
|
|
528 |
|
|
529 |
{\em Examples of inaccurate specification of the protocol ???}.
|
|
530 |
|
|
531 |
*}
|
|
532 |
|
|
533 |
section {* Conclusions \label{conclusion} *}
|
|
534 |
|
|
535 |
(*<*)
|
|
536 |
end
|
|
537 |
(*>*) |