--- a/thys2/zre7.sc	Thu Jan 20 01:48:18 2022 +0000
+++ b/thys2/zre7.sc	Sat Jan 22 10:48:09 2022 +0000
@@ -358,19 +358,19 @@
 //println(actualZipperSize(re1S))
 
 
-// val re2 = SEQ(ONE, "a")
-// val re2res = lex(re2, "a")
+mems.clear()
+val re2 = ALT("a", "bc")
+val re2res = lex(re2, "a")
 // //lex(1~a, "a") --> lexRecurse((1v, m  (SeqC(m (RootC, Nil), Nil, [1~a] ) )))
 
 
-// println(re2res)
+println(re2res)
 
-// val re2resPlugged = plug_all(re2res)
-// re2resPlugged.foreach(v => {
-//         val Sequ(Empty, vp) = v
-//         println(vp)
-// }
-// )
+val re2resPlugged = plug_all(re2res)
+ re2resPlugged.foreach(v => {
+         val Sequ(Empty, vp) = v
+         println(vp)
+}) 
 
 // println("remaining regex")
 // println(re1ss.flatMap(z => zipBackMem(z._2)))