thys2/zre7.sc
changeset 393 3954579ebdaf
parent 391 549257d0b8b2
child 394 4b22587fb667
equal deleted inserted replaced
392:8194086c2a8a 393:3954579ebdaf
   356 //println(re1ss)
   356 //println(re1ss)
   357 val re1S = zipperSimp(re1ss)
   357 val re1S = zipperSimp(re1ss)
   358 //println(actualZipperSize(re1S))
   358 //println(actualZipperSize(re1S))
   359 
   359 
   360 
   360 
   361 // val re2 = SEQ(ONE, "a")
   361 mems.clear()
   362 // val re2res = lex(re2, "a")
   362 val re2 = ALT("a", "bc")
       
   363 val re2res = lex(re2, "a")
   363 // //lex(1~a, "a") --> lexRecurse((1v, m  (SeqC(m (RootC, Nil), Nil, [1~a] ) )))
   364 // //lex(1~a, "a") --> lexRecurse((1v, m  (SeqC(m (RootC, Nil), Nil, [1~a] ) )))
   364 
   365 
   365 
   366 
   366 // println(re2res)
   367 println(re2res)
   367 
   368 
   368 // val re2resPlugged = plug_all(re2res)
   369 val re2resPlugged = plug_all(re2res)
   369 // re2resPlugged.foreach(v => {
   370  re2resPlugged.foreach(v => {
   370 //         val Sequ(Empty, vp) = v
   371          val Sequ(Empty, vp) = v
   371 //         println(vp)
   372          println(vp)
   372 // }
   373 }) 
   373 // )
       
   374 
   374 
   375 // println("remaining regex")
   375 // println("remaining regex")
   376 // println(re1ss.flatMap(z => zipBackMem(z._2)))
   376 // println(re1ss.flatMap(z => zipBackMem(z._2)))
   377 
   377 
   378 
   378