scala/comp1.scala
changeset 207 b93ec66cf4bb
parent 194 fc2a5e9fbb97
child 271 4457185b22ef
--- a/scala/comp1.scala	Fri Mar 01 11:16:30 2013 +0000
+++ b/scala/comp1.scala	Fri Mar 01 11:17:50 2013 +0000
@@ -56,7 +56,7 @@
 
 def compile_Goto(s: Int) = TMGoto.shift(s - 1)
 
-def compile(p: AProg, s: Int, i: AInst) = i match {
+def compile_abc(p: AProg, s: Int, i: AInst) = i match {
   case Inc(n) => compile_Inc(s, n)
   case Dec(n, e) => compile_Dec(s, n, address(p, e))
   case Goto(e) => compile_Goto(address(p, e))
@@ -64,7 +64,7 @@
 
 // component TMs for each instruction
 def TMs(p: AProg) = 
-  p.zipWithIndex.map{case (i, n) => compile(p, address(p, n), i)}
+  p.zipWithIndex.map{case (i, n) => compile_abc(p, address(p, n), i)}
 
 def toTM(p: AProg) = TMs(p).reduceLeft(_ ++ _)