--- a/index.html	Tue May 21 15:52:33 2024 +0100
+++ b/index.html	Tue Jan 07 12:42:42 2025 +0000
@@ -193,8 +193,8 @@
 by Xingyuan Zhang and me<BR>
 <p>
 
-<B>Current PhD</B> Chengsong Tan<BR>
-<B>Former PhD</B> Fahad Ausaf (works at ARM in the VHDL compiler team)<BR>
+<B>Current PhD</B> Meshal Nasser Binnasban<BR>  
+<B>Former PhDs</B> Fahad Ausaf (works at ARM in the VHDL compiler team); Chengsong Tan (postdoc at Imperial College, now works at <A HREF="https://www.kaihongdigi.com">Kaihong Digital</A> verifying OSes)<BR>
 <B>Former RAs</B> Chunhan Wu, <A HREF="http://cl-informatik.uibk.ac.at/users/cek/">Cezary Kaliszyk</A>, 
 <A HREF="http://dpt-info.u-strasbg.fr/~narboux/">Julien Narboux</A><p>