lex_blex_Frankensteined.scala
author Chengsong
Wed, 10 Jul 2019 23:16:14 +0100
changeset 72 83b021fc7d29
parent 59 8ff7b7508824
child 92 aaa2f2b52baf
permissions -rw-r--r--
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package RexpRelated
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import scala.language.implicitConversions    
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import scala.language.reflectiveCalls
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import scala.annotation.tailrec   
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import scala.util.Try
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abstract class Bit
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case object Z extends Bit
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case object S extends Bit
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//case class C(c: Char) extends Bit
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abstract class Rexp 
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case object ZERO extends Rexp
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case object ONE extends Rexp
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case class CHAR(c: Char) extends Rexp
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case class ALTS(rs: List[Rexp]) extends Rexp 
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case class SEQ(r1: Rexp, r2: Rexp) extends Rexp 
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case class STAR(r: Rexp) extends Rexp 
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case class RECD(x: String, r: Rexp) extends Rexp
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object Rexp{
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  type Bits = List[Bit]
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  // abbreviations
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  type Mon = (Char, Rexp)
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  type Lin = Set[Mon]
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  def ALT(r1: Rexp, r2: Rexp) = ALTS(List(r1, r2))
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  def PLUS(r: Rexp) = SEQ(r, STAR(r))
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  def AALT(bs: Bits, r1: ARexp, r2: ARexp) = AALTS(bs, List(r1, r2))
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  def distinctBy[B, C](xs: List[B], f: B => C, acc: List[C] = Nil): List[B] = xs match {
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    case Nil => Nil
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    case (x::xs) => {
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      val res = f(x)
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      if (acc.contains(res)) distinctBy(xs, f, acc)  
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      else x::distinctBy(xs, f, res::acc)
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    }
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  } 
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  // some convenience for typing in regular expressions
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  def charlist2rexp(s : List[Char]): Rexp = s match {
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    case Nil => ONE
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    case c::Nil => CHAR(c)
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    case c::s => SEQ(CHAR(c), charlist2rexp(s))
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  }
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  implicit def string2rexp(s : String) : Rexp = charlist2rexp(s.toList)
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  implicit def RexpOps(r: Rexp) = new {
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    def | (s: Rexp) = ALT(r, s)
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    def % = STAR(r)
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    def ~ (s: Rexp) = SEQ(r, s)
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  }
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  implicit def stringOps(s: String) = new {
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    def | (r: Rexp) = ALT(s, r)
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    def | (r: String) = ALT(s, r)
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    def % = STAR(s)
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    def ~ (r: Rexp) = SEQ(s, r)
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    def ~ (r: String) = SEQ(s, r)
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    def $ (r: Rexp) = RECD(s, r)
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  }
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  // translation into ARexps
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  def fuse(bs: Bits, r: ARexp) : ARexp = r match {
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    case AZERO => AZERO
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    case AONE(cs) => AONE(bs ++ cs)
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    case ACHAR(cs, f) => ACHAR(bs ++ cs, f)
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    case AALTS(cs, rs) => AALTS(bs ++ cs, rs)
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    case ASEQ(cs, r1, r2) => ASEQ(bs ++ cs, r1, r2)
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    case ASTAR(cs, r) => ASTAR(bs ++ cs, r)
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  }
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  def internalise(r: Rexp) : ARexp = r match {
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    case ZERO => AZERO
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    case ONE => AONE(Nil)
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    case CHAR(c) => ACHAR(Nil, c)
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    case ALTS(List(r1, r2)) => 
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      AALTS(Nil, List(fuse(List(Z), internalise(r1)), fuse(List(S), internalise(r2))))
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    case ALTS(r1::rs) => {
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      val AALTS(Nil, rs2) = internalise(ALTS(rs))
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      AALTS(Nil, fuse(List(Z), internalise(r1)) :: rs2.map(fuse(List(S), _)))
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    }
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    case SEQ(r1, r2) => ASEQ(Nil, internalise(r1), internalise(r2))
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    case STAR(r) => ASTAR(Nil, internalise(r))
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    case RECD(x, r) => internalise(r)
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  }
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  internalise(("a" | "ab") ~ ("b" | ""))
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  def decode_aux(r: Rexp, bs: Bits) : (Val, Bits) = (r, bs) match {
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    case (ONE, bs) => (Empty, bs)
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    case (CHAR(f), bs) => (Chr(f), bs)
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    case (ALTS(r::Nil), bs) => decode_aux(r, bs)//this case seems only used when we simp a regex before derivatives and it contains things like alt("a")
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    case (ALTS(rs), bs) => bs match {
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      case Z::bs1 => {
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        val (v, bs2) = decode_aux(rs.head, bs1)
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        (Left(v), bs2)
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      }
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      case S::bs1 => {
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        val (v, bs2) = decode_aux(ALTS(rs.tail), bs1)
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        (Right(v), bs2)			
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      }
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    }
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    case (SEQ(r1, r2), bs) => {
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      val (v1, bs1) = decode_aux(r1, bs)
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      val (v2, bs2) = decode_aux(r2, bs1)
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      (Sequ(v1, v2), bs2)
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    }
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    case (STAR(r1), S::bs) => {
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      val (v, bs1) = decode_aux(r1, bs)
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      //println(v)
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      val (Stars(vs), bs2) = decode_aux(STAR(r1), bs1)
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      (Stars(v::vs), bs2)
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    }
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    case (STAR(_), Z::bs) => (Stars(Nil), bs)
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    case (RECD(x, r1), bs) => {
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      val (v, bs1) = decode_aux(r1, bs)
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      (Rec(x, v), bs1)
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    }
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  }
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  def decode(r: Rexp, bs: Bits) = decode_aux(r, bs) match {
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    case (v, Nil) => v
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    case _ => throw new Exception("Not decodable")
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  }
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  def code(v: Val): Bits = v match {
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    case Empty => Nil
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    case Chr(a) => Nil
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    case Left(v) => Z :: code(v)
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    case Right(v) => S :: code(v)
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    case Sequ(v1, v2) => code(v1) ::: code(v2)
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    case Stars(Nil) => Z::Nil
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    case Stars(v::vs) => S::code(v) ::: code(Stars(vs))
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  }
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  def retrieve(r: ARexp, v: Val): Bits = (r,v) match {
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    case (AONE(bs), Empty) => bs
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    case (ACHAR(bs, c), Chr(d)) => bs
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    case (AALTS(bs, a::Nil), v) => bs ++ retrieve(a, v)
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    case (AALTS(bs, as), Left(v)) => bs ++ retrieve(as.head,v)
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    case (AALTS(bs, as), Right(v)) => bs ++ retrieve(AALTS(Nil,as.tail),v)
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    case (ASEQ(bs, a1, a2), Sequ(v1, v2)) => bs ++ retrieve(a1, v1) ++ retrieve(a2, v2)
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    case (ASTAR(bs, a), Stars(Nil)) => bs ++ List(Z) 
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    case (ASTAR(bs, a), Stars(v::vs)) => bs ++ List(S) ++ retrieve(a, v) ++ retrieve(ASTAR(Nil, a), Stars(vs))
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  }//bug here last clause should not add list(S)
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  //erase function: extracts the regx from Aregex
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  def erase(r:ARexp): Rexp = r match{
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    case AZERO => ZERO
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    case AONE(_) => ONE
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    case ACHAR(bs, f) => CHAR(f)
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    case AALTS(bs, rs) => ALTS(rs.map(erase(_)))
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    case ASEQ(bs, r1, r2) => SEQ (erase(r1), erase(r2))
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    case ASTAR(cs, r)=> STAR(erase(r))
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  }
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  //--------------------------------------------------------------------------------------------------------START OF NON-BITCODE PART
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  // nullable function: tests whether the regular 
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  // expression can recognise the empty string
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  def nullable (r: Rexp) : Boolean = r match {
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    case ZERO => false
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    case ONE => true
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    case CHAR(_) => false
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    case ALTS(rs) => rs.exists(nullable)
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    case SEQ(r1, r2) => nullable(r1) && nullable(r2)
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    case STAR(_) => true
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    case RECD(_, r) => nullable(r)
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    //case PLUS(r) => nullable(r)
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  }
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  // derivative of a regular expression w.r.t. a character
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  def der (c: Char, r: Rexp) : Rexp = r match {
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    case ZERO => ZERO
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    case ONE => ZERO
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    case CHAR(f) => if (c == f) ONE else ZERO
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    case ALTS(List(r1, r2)) => ALTS(List(der(c, r1), der(c, r2)))
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    case SEQ(r1, r2) => 
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      if (nullable(r1)) ALTS(List(SEQ(der(c, r1), r2), der(c, r2)))
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      else SEQ(der(c, r1), r2)
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    case STAR(r) => SEQ(der(c, r), STAR(r))
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    case RECD(_, r1) => der(c, r1)
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    //case PLUS(r) => SEQ(der(c, r), STAR(r))
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  }
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  def flatten(v: Val) : String = v match {
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    case Empty => ""
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    case Chr(c) => c.toString
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    case Left(v) => flatten(v)
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    case Right(v) => flatten(v)
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    case Sequ(v1, v2) => flatten(v1) + flatten(v2)
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    case Stars(vs) => vs.map(flatten).mkString
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    case Rec(_, v) => flatten(v)
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  }
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  // extracts an environment from a value
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  def env(v: Val) : List[(String, String)] = v match {
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    case Empty => Nil
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    case Chr(c) => Nil
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    case Left(v) => env(v)
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    case Right(v) => env(v)
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    case Sequ(v1, v2) => env(v1) ::: env(v2)
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    case Stars(vs) => vs.flatMap(env)
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    case Rec(x, v) => (x, flatten(v))::env(v)
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  }
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  // injection part
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  def mkeps(r: Rexp) : Val = r match {
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    case ONE => Empty
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    case ALTS(List(r1, r2)) => 
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      if (nullable(r1)) Left(mkeps(r1)) else Right(mkeps(r2))
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    case SEQ(r1, r2) => Sequ(mkeps(r1), mkeps(r2))
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    case STAR(r) => Stars(Nil)
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    case RECD(x, r) => Rec(x, mkeps(r))
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    //case PLUS(r) => Stars(List(mkeps(r)))
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  }
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  def inj(r: Rexp, c: Char, v: Val) : Val = (r, v) match {
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    case (STAR(r), Sequ(v1, Stars(vs))) => Stars(inj(r, c, v1)::vs)
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    case (SEQ(r1, r2), Sequ(v1, v2)) => Sequ(inj(r1, c, v1), v2)
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    case (SEQ(r1, r2), Left(Sequ(v1, v2))) => Sequ(inj(r1, c, v1), v2)
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    case (SEQ(r1, r2), Right(v2)) => Sequ(mkeps(r1), inj(r2, c, v2))
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    case (ALTS(List(r1, r2)), Left(v1)) => Left(inj(r1, c, v1))
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    case (ALTS(List(r1, r2)), Right(v2)) => Right(inj(r2, c, v2))
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    case (CHAR(_), Empty) => Chr(c) 
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    case (RECD(x, r1), _) => Rec(x, inj(r1, c, v))
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    //case (PLUS(r), Sequ(v1, Stars(vs))) => Stars(inj(r, c, v1)::vs)
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  }
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  def lex(r: Rexp, s: List[Char]) : Val = s match {
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    case Nil => if (nullable(r)) mkeps(r) else throw new Exception("Not matched")
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    case c::cs => inj(r, c, lex(der(c, r), cs))
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  }
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  def lexing(r: Rexp, s: String) : Val = lex(r, s.toList)
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  // some "rectification" functions for simplification
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  def F_ID(v: Val): Val = v
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  def F_RIGHT(f: Val => Val) = (v:Val) => Right(f(v))
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  def F_LEFT(f: Val => Val) = (v:Val) => Left(f(v))
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  def F_ALT(f1: Val => Val, f2: Val => Val) = (v:Val) => v match {
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    case Right(v) => Right(f2(v))
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    case Left(v) => Left(f1(v))
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  }
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  def F_SEQ(f1: Val => Val, f2: Val => Val) = (v:Val) => v match {
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    case Sequ(v1, v2) => Sequ(f1(v1), f2(v2))
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  }
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  def F_SEQ_Empty1(f1: Val => Val, f2: Val => Val) = 
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    (v:Val) => Sequ(f1(Empty), f2(v))
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  def F_SEQ_Empty2(f1: Val => Val, f2: Val => Val) = 
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    (v:Val) => Sequ(f1(v), f2(Empty))
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  def F_RECD(f: Val => Val) = (v:Val) => v match {
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    case Rec(x, v) => Rec(x, f(v))
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  }
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  def F_ERROR(v: Val): Val = throw new Exception("error")
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  // simplification of regular expressions returning also an
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  // rectification function; no simplification under STAR 
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  def simp(r: Rexp): (Rexp, Val => Val) = r match {
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    case ALTS(List(r1, r2)) => {
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      val (r1s, f1s) = simp(r1)
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      val (r2s, f2s) = simp(r2)
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      (r1s, r2s) match {
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        case (ZERO, _) => (r2s, F_RIGHT(f2s))
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        case (_, ZERO) => (r1s, F_LEFT(f1s))
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        case _ => if (r1s == r2s) (r1s, F_LEFT(f1s))
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                  else (ALTS(List(r1s, r2s)), F_ALT(f1s, f2s)) 
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      }
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    }
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    case SEQ(r1, r2) => {
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      val (r1s, f1s) = simp(r1)
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      val (r2s, f2s) = simp(r2)
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      (r1s, r2s) match {
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        case (ZERO, _) => (ZERO, F_ERROR)
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        case (_, ZERO) => (ZERO, F_ERROR)
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        case (ONE, _) => (r2s, F_SEQ_Empty1(f1s, f2s))
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        case (_, ONE) => (r1s, F_SEQ_Empty2(f1s, f2s))
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        case _ => (SEQ(r1s,r2s), F_SEQ(f1s, f2s))
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      }
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   282
    }
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    case RECD(x, r1) => {
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   284
      val (r1s, f1s) = simp(r1)
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   285
      (RECD(x, r1s), F_RECD(f1s))
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    }
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    case r => (r, F_ID)
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  }
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  /*
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  val each_simp_time = scala.collection.mutable.ArrayBuffer.empty[Long]
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  val each_simp_timeb = scala.collection.mutable.ArrayBuffer.empty[Long]
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  */
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  def lex_simp(r: Rexp, s: List[Char]) : Val = s match {
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   294
    case Nil => {
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   295
      if (nullable(r)) {
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   296
        mkeps(r) 
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   297
      }
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      else throw new Exception("Not matched")
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    }
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    case c::cs => {
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   301
      val (r_simp, f_simp) = simp(der(c, r))
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      inj(r, c, f_simp(lex_simp(r_simp, cs)))
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   303
    }
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   304
  }
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  def lexing_simp(r: Rexp, s: String) : Val = lex_simp(r, s.toList)
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  //println(lexing_simp(("a" | "ab") ~ ("b" | ""), "ab"))
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  // filters out all white spaces
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  def tokenise(r: Rexp, s: String) = 
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    env(lexing_simp(r, s)).filterNot { _._1 == "w"}
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  //reads the string from a file 
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  def fromFile(name: String) : String = 
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    io.Source.fromFile(name).mkString
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   318
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  def tokenise_file(r: Rexp, name: String) = 
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   320
    tokenise(r, fromFile(name))
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  //   Testing
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  //============
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   324
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  def time[T](code: => T) = {
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   326
    val start = System.nanoTime()
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    val result = code
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    val end = System.nanoTime()
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    println((end - start)/1.0e9)
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   330
    result
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   331
  }
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  //--------------------------------------------------------------------------------------------------------END OF NON-BITCODE PART
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  // bnullable function: tests whether the aregular 
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  // expression can recognise the empty string
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  def bnullable (r: ARexp) : Boolean = r match {
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   338
    case AZERO => false
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   339
    case AONE(_) => true
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    case ACHAR(_,_) => false
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   341
    case AALTS(_, rs) => rs.exists(bnullable)
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   342
    case ASEQ(_, r1, r2) => bnullable(r1) && bnullable(r2)
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   343
    case ASTAR(_, _) => true
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   344
  }
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   345
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   346
  def mkepsBC(r: ARexp) : Bits = r match {
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   347
    case AONE(bs) => bs
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   348
    case AALTS(bs, rs) => {
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   349
      val n = rs.indexWhere(bnullable)
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   350
      bs ++ mkepsBC(rs(n))
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   351
    }
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   352
    case ASEQ(bs, r1, r2) => bs ++ mkepsBC(r1) ++ mkepsBC(r2)
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   353
    case ASTAR(bs, r) => bs ++ List(Z)
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   354
  }
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   355
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   356
  // derivative of a regular expression w.r.t. a character
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   357
  def bder(c: Char, r: ARexp) : ARexp = r match {
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   358
    case AZERO => AZERO
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   359
    case AONE(_) => AZERO
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768b833d6230 removed C(c) The retrieve and code in the previous version is still not correct and will crash. no prob now.
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   360
    case ACHAR(bs, f) => if (c == f) AONE(bs) else AZERO
0
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diff changeset
   361
    case AALTS(bs, rs) => AALTS(bs, rs.map(bder(c, _)))
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   362
    case ASEQ(bs, r1, r2) => 
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   363
      if (bnullable(r1)) AALT(bs, ASEQ(Nil, bder(c, r1), r2), fuse(mkepsBC(r1), bder(c, r2)))
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   364
      else ASEQ(bs, bder(c, r1), r2)
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diff changeset
   365
    case ASTAR(bs, r) => ASEQ(bs, fuse(List(S), bder(c, r)), ASTAR(Nil, r))
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diff changeset
   366
  }
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   367
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diff changeset
   368
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   369
  def ders (s: List[Char], r: Rexp) : Rexp = s match {
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   370
    case Nil => r
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diff changeset
   371
    case c::s => ders(s, der(c, r))
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diff changeset
   372
  }
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diff changeset
   373
Chengsong
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diff changeset
   374
  // derivative w.r.t. a string (iterates bder)
Chengsong
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diff changeset
   375
  @tailrec
Chengsong
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diff changeset
   376
  def bders (s: List[Char], r: ARexp) : ARexp = s match {
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diff changeset
   377
    case Nil => r
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diff changeset
   378
    case c::s => bders(s, bder(c, r))
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diff changeset
   379
  }
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diff changeset
   380
Chengsong
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diff changeset
   381
  def flats(rs: List[ARexp]): List[ARexp] = rs match {
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diff changeset
   382
      case Nil => Nil
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diff changeset
   383
      case AZERO :: rs1 => flats(rs1)
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diff changeset
   384
      case AALTS(bs, rs1) :: rs2 => rs1.map(fuse(bs, _)) ::: flats(rs2)
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diff changeset
   385
      case r1 :: rs2 => r1 :: flats(rs2)
15
Chengsong
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diff changeset
   386
  }
17
Chengsong
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diff changeset
   387
  /*
15
Chengsong
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diff changeset
   388
  def remove(v: Val): Val = v match{
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diff changeset
   389
    case Right(v1) => v1
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diff changeset
   390
    case Left(v1) => v1
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diff changeset
   391
    case _ => throw new Exception("Not removable")
17
Chengsong
parents: 16
diff changeset
   392
  }*/
15
Chengsong
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diff changeset
   393
  def augment(v: Val, i: Int): Val = if(i > 1) augment(Right(v), i - 1) else Right(v)
Chengsong
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diff changeset
   394
//an overly complex version
Chengsong
parents: 14
diff changeset
   395
/*
Chengsong
parents: 14
diff changeset
   396
    if(rel_dist >0){//the regex we are dealing with is not what v points at
Chengsong
parents: 14
diff changeset
   397
      rs match{
Chengsong
parents: 14
diff changeset
   398
        case Nil => throw new Exception("Trying to simplify a non-existent value")
Chengsong
parents: 14
diff changeset
   399
        case AZERO :: rs1 => flats_vsimp(rs1, rel_dist - 1, remove(v))
Chengsong
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diff changeset
   400
        case AALTS(bs, rs1) :: rs2 => flats_vsimp(rs2, rel_dist - 1, augment(v, rs1.length - 1))//rs1 is guaranteed to have a len geq 2
Chengsong
parents: 14
diff changeset
   401
        case r1 :: rs2 => flats_vsimp(rs2, rel_dist - 1, v)
Chengsong
parents: 14
diff changeset
   402
      }
0
Chengsong
parents:
diff changeset
   403
    }
15
Chengsong
parents: 14
diff changeset
   404
    else if(rel_dist == 0){//we are dealing with regex v is pointing to -- "v->r itself"
Chengsong
parents: 14
diff changeset
   405
      rs match{//r1 cannot be zero
Chengsong
parents: 14
diff changeset
   406
        AALTS(bs, rs1) :: rs2 => flats_vsimp(  )
Chengsong
parents: 14
diff changeset
   407
        AZERO::rs2 => throw new Exception("Value corresponds to zero")
Chengsong
parents: 14
diff changeset
   408
        r1::rs2 => flats_vsimp(rs2, rel_dist - 1, v)
Chengsong
parents: 14
diff changeset
   409
      }
Chengsong
parents: 14
diff changeset
   410
Chengsong
parents: 14
diff changeset
   411
    }
Chengsong
parents: 14
diff changeset
   412
    else{
Chengsong
parents: 14
diff changeset
   413
Chengsong
parents: 14
diff changeset
   414
    }
Chengsong
parents: 14
diff changeset
   415
    */
Chengsong
parents: 14
diff changeset
   416
  def flats_vsimp(rs: List[ARexp], position: Int): Int = (rs, position) match {
Chengsong
parents: 14
diff changeset
   417
    case (_, 0) => 0
Chengsong
parents: 14
diff changeset
   418
    case (Nil, _) => 0
16
c51178fa85fe new version of slides
Chengsong
parents: 15
diff changeset
   419
    case (AZERO :: rs1, _) => flats_vsimp(rs1, position - 1) - 1
15
Chengsong
parents: 14
diff changeset
   420
    case (AALTS(bs, rs1) :: rs2, _) => rs1.length - 1 + flats_vsimp(rs2, position - 1)
Chengsong
parents: 14
diff changeset
   421
    case (r1 :: rs2, _) => flats_vsimp(rs2, position - 1)
Chengsong
parents: 14
diff changeset
   422
  }
0
Chengsong
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diff changeset
   423
  def rflats(rs: List[Rexp]): List[Rexp] = rs match {
Chengsong
parents:
diff changeset
   424
    case Nil => Nil
Chengsong
parents:
diff changeset
   425
    case ZERO :: rs1 => rflats(rs1)
Chengsong
parents:
diff changeset
   426
    case ALTS(rs1) :: rs2 => rs1 ::: rflats(rs2)
Chengsong
parents:
diff changeset
   427
    case r1 :: rs2 => r1 :: rflats(rs2)
Chengsong
parents:
diff changeset
   428
  }
Chengsong
parents:
diff changeset
   429
  var flats_time = 0L
Chengsong
parents:
diff changeset
   430
  var dist_time = 0L
Chengsong
parents:
diff changeset
   431
  
Chengsong
parents:
diff changeset
   432
  def bsimp(r: ARexp): ARexp = r match {
Chengsong
parents:
diff changeset
   433
    case ASEQ(bs1, r1, r2) => (bsimp(r1), bsimp(r2)) match {
Chengsong
parents:
diff changeset
   434
        case (AZERO, _) => AZERO
Chengsong
parents:
diff changeset
   435
        case (_, AZERO) => AZERO
Chengsong
parents:
diff changeset
   436
        case (AONE(bs2), r2s) => fuse(bs1 ++ bs2, r2s)
Chengsong
parents:
diff changeset
   437
        case (r1s, r2s) => ASEQ(bs1, r1s, r2s)
Chengsong
parents:
diff changeset
   438
    }
Chengsong
parents:
diff changeset
   439
    case AALTS(bs1, rs) => {
Chengsong
parents:
diff changeset
   440
      val rs_simp = rs.map(bsimp)
Chengsong
parents:
diff changeset
   441
      val flat_res = flats(rs_simp)
Chengsong
parents:
diff changeset
   442
      val dist_res = distinctBy(flat_res, erase)
Chengsong
parents:
diff changeset
   443
      dist_res match {
Chengsong
parents:
diff changeset
   444
        case Nil => AZERO
Chengsong
parents:
diff changeset
   445
        case s :: Nil => fuse(bs1, s)
Chengsong
parents:
diff changeset
   446
        case rs => AALTS(bs1, rs)  
Chengsong
parents:
diff changeset
   447
      }
Chengsong
parents:
diff changeset
   448
    }
5
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   449
    //case ASTAR(bs, r) => ASTAR(bs, bsimp(r))
0
Chengsong
parents:
diff changeset
   450
    case r => r
Chengsong
parents:
diff changeset
   451
  }
17
Chengsong
parents: 16
diff changeset
   452
  def find_pos(v: Val, rs: List[ARexp]): Int = (v, rs) match{
Chengsong
parents: 16
diff changeset
   453
    case (v, r::Nil) => 0
15
Chengsong
parents: 14
diff changeset
   454
    case (Right(v), r::rs) => find_pos(v, rs) + 1
17
Chengsong
parents: 16
diff changeset
   455
    case (Left(v), r::rs) => 0
Chengsong
parents: 16
diff changeset
   456
    //case (v, _) => 0
Chengsong
parents: 16
diff changeset
   457
  }
Chengsong
parents: 16
diff changeset
   458
  def find_pos_aux(v: Val, r: ARexp): Int = r match {
Chengsong
parents: 16
diff changeset
   459
    case AALTS(bs, rs) => find_pos(v, rs)
Chengsong
parents: 16
diff changeset
   460
    case r => 0
15
Chengsong
parents: 14
diff changeset
   461
  }
17
Chengsong
parents: 16
diff changeset
   462
  def remove(v: Val, rs: List[ARexp]) : Val = (v,rs) match {//remove the outmost layer of ALTS's Left and Right
Chengsong
parents: 16
diff changeset
   463
    //we have to use r to detect the bound of nested L/Rs
Chengsong
parents: 16
diff changeset
   464
    case (v, r::Nil) => v
Chengsong
parents: 16
diff changeset
   465
    case (Right(v), r::rs) => remove(v, rs) 
15
Chengsong
parents: 14
diff changeset
   466
    case (Left(v), r::rs) => v 
17
Chengsong
parents: 16
diff changeset
   467
    //case (v, r::Nil) => v
15
Chengsong
parents: 14
diff changeset
   468
  }
16
c51178fa85fe new version of slides
Chengsong
parents: 15
diff changeset
   469
  def simple_end(v: Val): Boolean = v match {
15
Chengsong
parents: 14
diff changeset
   470
    case Left(v) => return false
Chengsong
parents: 14
diff changeset
   471
    case Right(v) => return simple_end(v)
Chengsong
parents: 14
diff changeset
   472
    case v => return true
Chengsong
parents: 14
diff changeset
   473
  }
17
Chengsong
parents: 16
diff changeset
   474
  def isend(v: Val, rs: List[ARexp], position: Int): Boolean = {//TODO: here the slice api i am not familiar with so this call might be incorrect and crash the bsimp2
Chengsong
parents: 16
diff changeset
   475
    val rsbh = rs.slice(position + 1, rs.length)
15
Chengsong
parents: 14
diff changeset
   476
    val out_end = if(flats(rsbh) == Nil) true else false
Chengsong
parents: 14
diff changeset
   477
    val inner_end = simple_end(v)
Chengsong
parents: 14
diff changeset
   478
    inner_end && out_end
Chengsong
parents: 14
diff changeset
   479
  }
16
c51178fa85fe new version of slides
Chengsong
parents: 15
diff changeset
   480
  def get_coat(v: Val, rs: List[Rexp], vs: Val): Val = (v, rs) match{//the dual operation of remove(so-called by myself)
15
Chengsong
parents: 14
diff changeset
   481
    case (Right(v), r::Nil) => Right(vs)
Chengsong
parents: 14
diff changeset
   482
    case (Left(v), r::rs) => Left(vs) 
Chengsong
parents: 14
diff changeset
   483
    case (Right(v), r::rs) => Right(get_coat(v, rs, vs))
Chengsong
parents: 14
diff changeset
   484
  }
Chengsong
parents: 14
diff changeset
   485
  def coat(v: Val, i: Int) : Val = i match {
Chengsong
parents: 14
diff changeset
   486
    case 0 => v
Chengsong
parents: 14
diff changeset
   487
    case i => coat(Right(v), i - 1)
Chengsong
parents: 14
diff changeset
   488
  }
17
Chengsong
parents: 16
diff changeset
   489
  //This version takes a regex and a value, return a simplified regex and its corresponding simplified value 
Chengsong
parents: 16
diff changeset
   490
  def bsimp2(r: ARexp, v: Val): (ARexp, Val) = (r,v) match{
Chengsong
parents: 16
diff changeset
   491
    case (ASEQ(bs1, r1, r2), Sequ(v1, v2)) => (bsimp2(r1, v1), bsimp2(r2, v2)) match {
Chengsong
parents: 16
diff changeset
   492
        case ((AZERO, _), (_, _) )=> (AZERO, undefined)
Chengsong
parents: 16
diff changeset
   493
        case ((_, _), (AZERO, _)) => (AZERO, undefined)
Chengsong
parents: 16
diff changeset
   494
        case ((AONE(bs2), v1s) , (r2s, v2s)) => (fuse(bs1 ++ bs2, r2s), v2s )//v2 tells how to retrieve bits in r2s, which is enough as the bits of the first part of the sequence has already been integrated to the top level of the second regx.
Chengsong
parents: 16
diff changeset
   495
        case ((r1s, v1s), (r2s, v2s)) => (ASEQ(bs1, r1s, r2s),  Sequ(v1s, v2s))
Chengsong
parents: 16
diff changeset
   496
    }
Chengsong
parents: 16
diff changeset
   497
    case (AALTS(bs1, rs), v) => {
Chengsong
parents: 16
diff changeset
   498
      //phase 1 transformation so that aalts(bs1, rs) => aalts(bs1, rsf) and v => vf
Chengsong
parents: 16
diff changeset
   499
      val init_ind = find_pos(v, rs)
Chengsong
parents: 16
diff changeset
   500
      //println(rs)
Chengsong
parents: 16
diff changeset
   501
      //println(v)
Chengsong
parents: 16
diff changeset
   502
      val vs = bsimp2(rs(init_ind), remove(v, rs))//remove all the outer layers of left and right in v to  match the regx rs[i]
Chengsong
parents: 16
diff changeset
   503
      //println(vs)
Chengsong
parents: 16
diff changeset
   504
      val rs_simp = rs.map(bsimp)
Chengsong
parents: 16
diff changeset
   505
      val vs_kernel = rs_simp(init_ind) match {
Chengsong
parents: 16
diff changeset
   506
        case AALTS(bs2, rs2) => remove(vs._2, rs2)//remove the secondary layer of left and right
Chengsong
parents: 16
diff changeset
   507
        case r => vs._2
Chengsong
parents: 16
diff changeset
   508
      }
Chengsong
parents: 16
diff changeset
   509
      val flat_res = flats(rs_simp)
Chengsong
parents: 16
diff changeset
   510
      //println(rs_simp)
Chengsong
parents: 16
diff changeset
   511
      //println(flat_res)
Chengsong
parents: 16
diff changeset
   512
      //println(init_ind)
Chengsong
parents: 16
diff changeset
   513
      val vs_for_coating = if(isend(vs._2, rs_simp, init_ind)||flat_res.length == 1) vs_kernel else Left(vs_kernel)
Chengsong
parents: 16
diff changeset
   514
      //println(vs_for_coating)
Chengsong
parents: 16
diff changeset
   515
      val r_s = rs_simp(init_ind)//or vs._1
Chengsong
parents: 16
diff changeset
   516
      val shift = flats_vsimp(rs_simp, init_ind) + find_pos_aux(vs._2, rs_simp(init_ind))
Chengsong
parents: 16
diff changeset
   517
      //println(shift)
Chengsong
parents: 16
diff changeset
   518
      val new_ind = init_ind + shift
Chengsong
parents: 16
diff changeset
   519
      //println("new ind:")
Chengsong
parents: 16
diff changeset
   520
      //println(new_ind)
Chengsong
parents: 16
diff changeset
   521
      val vf = coat(vs_for_coating, new_ind)
Chengsong
parents: 16
diff changeset
   522
      //println("vf:")
Chengsong
parents: 16
diff changeset
   523
      //println(vf)
Chengsong
parents: 16
diff changeset
   524
      //flats2 returns a list of regex and a single v
Chengsong
parents: 16
diff changeset
   525
      //now |- vf: ALTS(bs1, flat_res)
Chengsong
parents: 16
diff changeset
   526
Chengsong
parents: 16
diff changeset
   527
      //phase 2 transformation so that aalts(bs1, rsf) => aalts(bs, rsdb) and vf => vdb
Chengsong
parents: 16
diff changeset
   528
      val dist_res = distinctBy(flat_res, erase)
Chengsong
parents: 16
diff changeset
   529
      val front_part = distinctBy(flat_res.slice(0, new_ind + 1), erase)
Chengsong
parents: 16
diff changeset
   530
      //val size_reduction = new_ind + 1 - front_part.length
Chengsong
parents: 16
diff changeset
   531
      //println(flat_res.length)
Chengsong
parents: 16
diff changeset
   532
      //println(dist_res)
Chengsong
parents: 16
diff changeset
   533
      //println(front_part)
Chengsong
parents: 16
diff changeset
   534
      val vdb = if(dist_res.length == front_part.length )//that means the regex we are interested in is at the end of the list
Chengsong
parents: 16
diff changeset
   535
      {
Chengsong
parents: 16
diff changeset
   536
        coat(vs_kernel, front_part.length - 1)
Chengsong
parents: 16
diff changeset
   537
      }
Chengsong
parents: 16
diff changeset
   538
      else{
Chengsong
parents: 16
diff changeset
   539
        coat(Left(vs_kernel), front_part.length - 1)
Chengsong
parents: 16
diff changeset
   540
      }
Chengsong
parents: 16
diff changeset
   541
      //println(vdb)
Chengsong
parents: 16
diff changeset
   542
      //we don't need to transform vdb as this phase will not make enough changes to the regex to affect value.
Chengsong
parents: 16
diff changeset
   543
      //the above statement needs verification. but can be left as is now.
Chengsong
parents: 16
diff changeset
   544
      dist_res match {
Chengsong
parents: 16
diff changeset
   545
        case Nil => (AZERO, undefined)
Chengsong
parents: 16
diff changeset
   546
        case s :: Nil => (fuse(bs1, s), vdb)
Chengsong
parents: 16
diff changeset
   547
        case rs => (AALTS(bs1, rs), vdb)
Chengsong
parents: 16
diff changeset
   548
      }
Chengsong
parents: 16
diff changeset
   549
    }
Chengsong
parents: 16
diff changeset
   550
    //case ASTAR(bs, r) => ASTAR(bs, bsimp(r))
Chengsong
parents: 16
diff changeset
   551
    case (r, v) => (r, v)  
Chengsong
parents: 16
diff changeset
   552
  }
Chengsong
parents: 16
diff changeset
   553
  def vsimp(r: ARexp, v: Val): Val = bsimp2(r, v)._2
Chengsong
parents: 16
diff changeset
   554
  /*This version was first intended for returning a function however a value would be simpler.
15
Chengsong
parents: 14
diff changeset
   555
  def bsimp2(r: ARexp, v: Val): (ARexp, Val => Val) = (r,v) match{
Chengsong
parents: 14
diff changeset
   556
    case (ASEQ(bs1, r1, r2), v) => (bsimp2(r1), bsimp2(r2)) match {
Chengsong
parents: 14
diff changeset
   557
        case ((AZERO, _), (_, _) )=> (AZERO, undefined)
Chengsong
parents: 14
diff changeset
   558
        case ((_, _), (AZERO, _)) => (AZERO, undefined)
Chengsong
parents: 14
diff changeset
   559
        case ((AONE(bs2), f1) , (r2s, f2)) => (fuse(bs1 ++ bs2, r2s), lambda v => v match { case Sequ(_, v) => f2(v) } )
Chengsong
parents: 14
diff changeset
   560
        case ((r1s, f1), (r2s, f2)) => (ASEQ(bs1, r1s, r2s), lambda v => v match {case Sequ(v1, v2) => Sequ(f1(v1), f2(v2))}
Chengsong
parents: 14
diff changeset
   561
    }
Chengsong
parents: 14
diff changeset
   562
    case AALTS(bs1, rs) => {
Chengsong
parents: 14
diff changeset
   563
      val init_ind = find_pos(v, rs)
Chengsong
parents: 14
diff changeset
   564
      val vs = bsimp2(rs[init_ind], remove(v, rs))//remove all the outer layers of left and right in v to  match the regx rs[i]
Chengsong
parents: 14
diff changeset
   565
      val rs_simp = rs.map(bsimp)
Chengsong
parents: 14
diff changeset
   566
      val vs_kernel = rs_simp[init_ind] match {
Chengsong
parents: 14
diff changeset
   567
        case AALTS(bs2, rs2) => remove(vs, rs_simp[init_ind])//remove the secondary layer of left and right
Chengsong
parents: 14
diff changeset
   568
        case r => vs
Chengsong
parents: 14
diff changeset
   569
      }
Chengsong
parents: 14
diff changeset
   570
      val vs_for_coating = if(isend(vs, rs_simp, init_ind)) vs_kernel else Left(vs_kernel)
Chengsong
parents: 14
diff changeset
   571
Chengsong
parents: 14
diff changeset
   572
      val r_s = rs_simp[init_ind]
Chengsong
parents: 14
diff changeset
   573
      val shift = flats_vsimp(vs, rs_simp, init_ind) + find_pos(vs, rs_simp[init_ind])
Chengsong
parents: 14
diff changeset
   574
      val vf = coat(vs_for_coating, shift + init_ind)
Chengsong
parents: 14
diff changeset
   575
Chengsong
parents: 14
diff changeset
   576
      val flat_res = flats(rs_simp)//flats2 returns a list of regex and a single v
Chengsong
parents: 14
diff changeset
   577
      val dist_res = distinctBy(flat_res, erase)
Chengsong
parents: 14
diff changeset
   578
      dist_res match {
Chengsong
parents: 14
diff changeset
   579
        case Nil => AZERO
Chengsong
parents: 14
diff changeset
   580
        case s :: Nil => fuse(bs1, s)
Chengsong
parents: 14
diff changeset
   581
        case rs => AALTS(bs1, rs)  
Chengsong
parents: 14
diff changeset
   582
      }
Chengsong
parents: 14
diff changeset
   583
    }
Chengsong
parents: 14
diff changeset
   584
    //case ASTAR(bs, r) => ASTAR(bs, bsimp(r))
Chengsong
parents: 14
diff changeset
   585
    case r => r  
16
c51178fa85fe new version of slides
Chengsong
parents: 15
diff changeset
   586
  }*/
5
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   587
  def super_bsimp(r: ARexp): ARexp = r match {
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   588
    case ASEQ(bs1, r1, r2) => (super_bsimp(r1), super_bsimp(r2)) match {
0
Chengsong
parents:
diff changeset
   589
        case (AZERO, _) => AZERO
Chengsong
parents:
diff changeset
   590
        case (_, AZERO) => AZERO
11
9c1ca6d6e190 The C(Char) construct is incompatible with the code and retrieve in Fahad's thesis.
Chengsong
parents: 5
diff changeset
   591
        case (AONE(bs2), r2s) => fuse(bs1 ++ bs2, r2s)//万一是(r1, alts(rs))这种形式呢
9c1ca6d6e190 The C(Char) construct is incompatible with the code and retrieve in Fahad's thesis.
Chengsong
parents: 5
diff changeset
   592
        case (AALTS(bs2, rs), r2) => AALTS(bs1 ++ bs2, rs.map(r => r match {case AONE(bs3) => fuse(bs3, r2) case r => ASEQ(Nil, r, r2)} ) ) 
0
Chengsong
parents:
diff changeset
   593
        case (r1s, r2s) => ASEQ(bs1, r1s, r2s)
Chengsong
parents:
diff changeset
   594
    }
Chengsong
parents:
diff changeset
   595
    case AALTS(bs1, rs) => {
5
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   596
      val rs_simp = rs.map(super_bsimp)
0
Chengsong
parents:
diff changeset
   597
      val flat_res = flats(rs_simp)
Chengsong
parents:
diff changeset
   598
      val dist_res = distinctBy(flat_res, erase)
Chengsong
parents:
diff changeset
   599
      dist_res match {
Chengsong
parents:
diff changeset
   600
        case Nil => AZERO
Chengsong
parents:
diff changeset
   601
        case s :: Nil => fuse(bs1, s)
Chengsong
parents:
diff changeset
   602
        case rs => AALTS(bs1, rs)  
Chengsong
parents:
diff changeset
   603
      }
Chengsong
parents:
diff changeset
   604
    }
5
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   605
    //case ASTAR(bs, r) => ASTAR(bs, bsimp(r))
0
Chengsong
parents:
diff changeset
   606
    case r => r
Chengsong
parents:
diff changeset
   607
  }
Chengsong
parents:
diff changeset
   608
5
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   609
0
Chengsong
parents:
diff changeset
   610
  def simp_weakened(r: Rexp): Rexp = r match {
Chengsong
parents:
diff changeset
   611
    case SEQ(r1, r2) => (simp_weakened(r1), r2) match {
Chengsong
parents:
diff changeset
   612
        case (ZERO, _) => ZERO
Chengsong
parents:
diff changeset
   613
        case (_, ZERO) => ZERO
Chengsong
parents:
diff changeset
   614
        case (ONE, r2s) => r2s
Chengsong
parents:
diff changeset
   615
        case (r1s, r2s) => SEQ(r1s, r2s)
Chengsong
parents:
diff changeset
   616
    }
Chengsong
parents:
diff changeset
   617
    case ALTS(rs) => {
Chengsong
parents:
diff changeset
   618
      val rs_simp = rs.map(simp_weakened)
Chengsong
parents:
diff changeset
   619
      val flat_res = rflats(rs_simp)
Chengsong
parents:
diff changeset
   620
      val dist_res = rs_simp.distinct
Chengsong
parents:
diff changeset
   621
      dist_res match {
Chengsong
parents:
diff changeset
   622
        case Nil => ZERO
Chengsong
parents:
diff changeset
   623
        case s :: Nil => s
Chengsong
parents:
diff changeset
   624
        case rs => ALTS(rs)  
Chengsong
parents:
diff changeset
   625
      }
Chengsong
parents:
diff changeset
   626
    }
Chengsong
parents:
diff changeset
   627
    case STAR(r) => STAR(simp_weakened(r))
Chengsong
parents:
diff changeset
   628
    case r => r
Chengsong
parents:
diff changeset
   629
  }
Chengsong
parents:
diff changeset
   630
    
Chengsong
parents:
diff changeset
   631
  def bders_simp (s: List[Char], r: ARexp) : ARexp = s match {
Chengsong
parents:
diff changeset
   632
    case Nil => r
Chengsong
parents:
diff changeset
   633
    case c::s => bders_simp(s, bsimp(bder(c, r)))
Chengsong
parents:
diff changeset
   634
  }
14
610f14009c0b the property
Chengsong
parents: 12
diff changeset
   635
  //----------------------------------------------------------------------------experiment bsimp
610f14009c0b the property
Chengsong
parents: 12
diff changeset
   636
  /*
610f14009c0b the property
Chengsong
parents: 12
diff changeset
   637
0
Chengsong
parents:
diff changeset
   638
  */
Chengsong
parents:
diff changeset
   639
  /*
Chengsong
parents:
diff changeset
   640
  def time[T](code: => T) = {
Chengsong
parents:
diff changeset
   641
    val start = System.nanoTime()
Chengsong
parents:
diff changeset
   642
    val result = code
Chengsong
parents:
diff changeset
   643
    val end = System.nanoTime()
Chengsong
parents:
diff changeset
   644
    println((end - start)/1.0e9)
Chengsong
parents:
diff changeset
   645
    result
Chengsong
parents:
diff changeset
   646
  }
Chengsong
parents:
diff changeset
   647
  */
Chengsong
parents:
diff changeset
   648
  // main unsimplified lexing function (produces a value)
Chengsong
parents:
diff changeset
   649
  def blex(r: ARexp, s: List[Char]) : Bits = s match {
Chengsong
parents:
diff changeset
   650
    case Nil => if (bnullable(r)) mkepsBC(r) else throw new Exception("Not matched")
Chengsong
parents:
diff changeset
   651
    case c::cs => {
Chengsong
parents:
diff changeset
   652
      val der_res = bder(c,r)
Chengsong
parents:
diff changeset
   653
      blex(der_res, cs)
Chengsong
parents:
diff changeset
   654
    }
Chengsong
parents:
diff changeset
   655
  }
Chengsong
parents:
diff changeset
   656
Chengsong
parents:
diff changeset
   657
  def bpre_lexing(r: Rexp, s: String) = blex(internalise(r), s.toList)
14
610f14009c0b the property
Chengsong
parents: 12
diff changeset
   658
  def blexing(r: Rexp, s: String) : Val = decode(r, blex(internalise(r), s.toList))
0
Chengsong
parents:
diff changeset
   659
Chengsong
parents:
diff changeset
   660
  var bder_time = 0L
Chengsong
parents:
diff changeset
   661
  var bsimp_time = 0L
Chengsong
parents:
diff changeset
   662
  var mkepsBC_time = 0L
Chengsong
parents:
diff changeset
   663
  var small_de = 2
Chengsong
parents:
diff changeset
   664
  var big_de = 5
Chengsong
parents:
diff changeset
   665
  var usual_de = 3
Chengsong
parents:
diff changeset
   666
  
Chengsong
parents:
diff changeset
   667
  def blex_simp(r: ARexp, s: List[Char]) : Bits = s match {
Chengsong
parents:
diff changeset
   668
    case Nil => {
Chengsong
parents:
diff changeset
   669
      if (bnullable(r)) {
Chengsong
parents:
diff changeset
   670
        //println(asize(r))
5
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   671
        mkepsBC(r)
0
Chengsong
parents:
diff changeset
   672
      }
Chengsong
parents:
diff changeset
   673
    else throw new Exception("Not matched")
Chengsong
parents:
diff changeset
   674
    }
Chengsong
parents:
diff changeset
   675
    case c::cs => {
Chengsong
parents:
diff changeset
   676
      val der_res = bder(c,r)
Chengsong
parents:
diff changeset
   677
      val simp_res = bsimp(der_res)
Chengsong
parents:
diff changeset
   678
      blex_simp(simp_res, cs)      
Chengsong
parents:
diff changeset
   679
    }
Chengsong
parents:
diff changeset
   680
  }
5
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   681
  def super_blex_simp(r: ARexp, s: List[Char]): Bits = s match {
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   682
    case Nil => {
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   683
      if (bnullable(r)) {
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   684
        mkepsBC(r)
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   685
      }
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   686
      else throw new Exception("Not matched")
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   687
    }
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   688
    case c::cs => {
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   689
      super_blex_simp(super_bsimp(bder(c,r)), cs)
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   690
    }
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   691
  }
0
Chengsong
parents:
diff changeset
   692
  def blex_real_simp(r: ARexp, s: List[Char]): ARexp = s match{
Chengsong
parents:
diff changeset
   693
    case Nil => r
Chengsong
parents:
diff changeset
   694
    case c::cs => blex_real_simp(bsimp(bder(c, r)), cs)
Chengsong
parents:
diff changeset
   695
  }
Chengsong
parents:
diff changeset
   696
Chengsong
parents:
diff changeset
   697
Chengsong
parents:
diff changeset
   698
  //size: of a Aregx for testing purposes 
Chengsong
parents:
diff changeset
   699
  def size(r: Rexp) : Int = r match {
Chengsong
parents:
diff changeset
   700
    case ZERO => 1
Chengsong
parents:
diff changeset
   701
    case ONE => 1
Chengsong
parents:
diff changeset
   702
    case CHAR(_) => 1
Chengsong
parents:
diff changeset
   703
    case SEQ(r1, r2) => 1 + size(r1) + size(r2)
Chengsong
parents:
diff changeset
   704
    case ALTS(rs) => 1 + rs.map(size).sum
Chengsong
parents:
diff changeset
   705
    case STAR(r) => 1 + size(r)
Chengsong
parents:
diff changeset
   706
  }
Chengsong
parents:
diff changeset
   707
Chengsong
parents:
diff changeset
   708
  def asize(a: ARexp) = size(erase(a))
Chengsong
parents:
diff changeset
   709
Chengsong
parents:
diff changeset
   710
Chengsong
parents:
diff changeset
   711
  // decoding does not work yet
Chengsong
parents:
diff changeset
   712
  def blexing_simp(r: Rexp, s: String) = {
Chengsong
parents:
diff changeset
   713
    val bit_code = blex_simp(internalise(r), s.toList)
5
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   714
    decode(r, bit_code) 
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   715
  }
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   716
  def super_blexing_simp(r: Rexp, s: String) = {
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   717
    decode(r, super_blex_simp(internalise(r), s.toList))
0
Chengsong
parents:
diff changeset
   718
  }
Chengsong
parents:
diff changeset
   719
Chengsong
parents:
diff changeset
   720
Chengsong
parents:
diff changeset
   721
Chengsong
parents:
diff changeset
   722
Chengsong
parents:
diff changeset
   723
Chengsong
parents:
diff changeset
   724
  // Lexing Rules for a Small While Language
Chengsong
parents:
diff changeset
   725
Chengsong
parents:
diff changeset
   726
  //symbols
Chengsong
parents:
diff changeset
   727
  /*
Chengsong
parents:
diff changeset
   728
  val SYM = PRED("abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ".contains(_))
Chengsong
parents:
diff changeset
   729
  
Chengsong
parents:
diff changeset
   730
  //digits
Chengsong
parents:
diff changeset
   731
  val DIGIT = PRED("0123456789".contains(_))
Chengsong
parents:
diff changeset
   732
  //identifiers
Chengsong
parents:
diff changeset
   733
  val ID = SYM ~ (SYM | DIGIT).% 
Chengsong
parents:
diff changeset
   734
  //numbers
Chengsong
parents:
diff changeset
   735
  val NUM = STAR(DIGIT)
Chengsong
parents:
diff changeset
   736
  //keywords
Chengsong
parents:
diff changeset
   737
  val KEYWORD : Rexp = "skip" | "while" | "do" | "if" | "then" | "else" | "read" | "write" | "true" | "false"
Chengsong
parents:
diff changeset
   738
  val AKEYWORD: Rexp = ALTS(List("skip" , "while" , "do" , "if" , "then" , "else" , "read" , "write" , "true" , "false"))
Chengsong
parents:
diff changeset
   739
  //semicolons
Chengsong
parents:
diff changeset
   740
  val SEMI: Rexp = ";"
Chengsong
parents:
diff changeset
   741
  //operators
Chengsong
parents:
diff changeset
   742
  val OP: Rexp = ":=" | "==" | "-" | "+" | "*" | "!=" | "<" | ">" | "<=" | ">=" | "%" | "/"
Chengsong
parents:
diff changeset
   743
  val AOP: Rexp = ALTS(List(":=" , "==" , "-" , "+" , "*" , "!=" , "<" , ">" , "<=" , ">=" , "%" , "/"))
Chengsong
parents:
diff changeset
   744
  //whitespaces
Chengsong
parents:
diff changeset
   745
  val WHITESPACE = PLUS(" " | "\n" | "\t")
Chengsong
parents:
diff changeset
   746
  //parentheses
Chengsong
parents:
diff changeset
   747
  val RPAREN: Rexp = ")"
Chengsong
parents:
diff changeset
   748
  val LPAREN: Rexp = "("
Chengsong
parents:
diff changeset
   749
  val BEGIN: Rexp = "{"
Chengsong
parents:
diff changeset
   750
  val END: Rexp = "}"
Chengsong
parents:
diff changeset
   751
  //strings...but probably needs not
Chengsong
parents:
diff changeset
   752
  val STRING: Rexp = "\"" ~ SYM.% ~ "\""
Chengsong
parents:
diff changeset
   753
Chengsong
parents:
diff changeset
   754
Chengsong
parents:
diff changeset
   755
Chengsong
parents:
diff changeset
   756
  val WHILE_REGS = (("k" $ KEYWORD) | 
Chengsong
parents:
diff changeset
   757
                    ("i" $ ID) | 
Chengsong
parents:
diff changeset
   758
                    ("o" $ OP) | 
Chengsong
parents:
diff changeset
   759
                    ("n" $ NUM) | 
Chengsong
parents:
diff changeset
   760
                    ("s" $ SEMI) | 
Chengsong
parents:
diff changeset
   761
                    ("str" $ STRING) |
Chengsong
parents:
diff changeset
   762
                    ("p" $ (LPAREN | RPAREN)) | 
Chengsong
parents:
diff changeset
   763
                    ("b" $ (BEGIN | END)) | 
Chengsong
parents:
diff changeset
   764
                    ("w" $ WHITESPACE)).%
Chengsong
parents:
diff changeset
   765
Chengsong
parents:
diff changeset
   766
  val AWHILE_REGS = (
Chengsong
parents:
diff changeset
   767
    ALTS(
Chengsong
parents:
diff changeset
   768
      List(
Chengsong
parents:
diff changeset
   769
        ("k" $ AKEYWORD), 
Chengsong
parents:
diff changeset
   770
                    ("i" $ ID),
Chengsong
parents:
diff changeset
   771
                    ("o" $ AOP) , 
Chengsong
parents:
diff changeset
   772
                    ("n" $ NUM) ,
Chengsong
parents:
diff changeset
   773
                    ("s" $ SEMI) ,
Chengsong
parents:
diff changeset
   774
                    ("str" $ STRING), 
Chengsong
parents:
diff changeset
   775
                    ("p" $ (LPAREN | RPAREN)), 
Chengsong
parents:
diff changeset
   776
                    ("b" $ (BEGIN | END)), 
Chengsong
parents:
diff changeset
   777
                    ("w" $ WHITESPACE)
Chengsong
parents:
diff changeset
   778
      )
Chengsong
parents:
diff changeset
   779
    )
Chengsong
parents:
diff changeset
   780
  ).%
Chengsong
parents:
diff changeset
   781
Chengsong
parents:
diff changeset
   782
*/
Chengsong
parents:
diff changeset
   783
Chengsong
parents:
diff changeset
   784
Chengsong
parents:
diff changeset
   785
  //--------------------------------------------------------------------------------------------------------START OF NON-BITCODE PART (TESTING)
Chengsong
parents:
diff changeset
   786
  /*
Chengsong
parents:
diff changeset
   787
  // Two Simple While programs
Chengsong
parents:
diff changeset
   788
  //========================
Chengsong
parents:
diff changeset
   789
  println("prog0 test")
Chengsong
parents:
diff changeset
   790
Chengsong
parents:
diff changeset
   791
  val prog0 = """read n"""
Chengsong
parents:
diff changeset
   792
  println(env(lexing_simp(WHILE_REGS, prog0)))
Chengsong
parents:
diff changeset
   793
  println(tokenise(WHILE_REGS, prog0))
Chengsong
parents:
diff changeset
   794
Chengsong
parents:
diff changeset
   795
  println("prog1 test")
Chengsong
parents:
diff changeset
   796
Chengsong
parents:
diff changeset
   797
  val prog1 = """read  n; write (n)"""
Chengsong
parents:
diff changeset
   798
  println(tokenise(WHILE_REGS, prog1))
Chengsong
parents:
diff changeset
   799
Chengsong
parents:
diff changeset
   800
  */
Chengsong
parents:
diff changeset
   801
  // Bigger Tests
Chengsong
parents:
diff changeset
   802
  //==============
Chengsong
parents:
diff changeset
   803
Chengsong
parents:
diff changeset
   804
  def escape(raw: String): String = {
Chengsong
parents:
diff changeset
   805
    import scala.reflect.runtime.universe._
Chengsong
parents:
diff changeset
   806
    Literal(Constant(raw)).toString
Chengsong
parents:
diff changeset
   807
  }
Chengsong
parents:
diff changeset
   808
Chengsong
parents:
diff changeset
   809
  val prog2 = """
Chengsong
parents:
diff changeset
   810
  write "Fib";
Chengsong
parents:
diff changeset
   811
  read n;
Chengsong
parents:
diff changeset
   812
  minus1 := 0;
Chengsong
parents:
diff changeset
   813
  minus2 := 1;
Chengsong
parents:
diff changeset
   814
  while n > 0 do {
Chengsong
parents:
diff changeset
   815
    temp := minus2;
Chengsong
parents:
diff changeset
   816
    minus2 := minus1 + minus2;
Chengsong
parents:
diff changeset
   817
    minus1 := temp;
Chengsong
parents:
diff changeset
   818
    n := n - 1
Chengsong
parents:
diff changeset
   819
  };
Chengsong
parents:
diff changeset
   820
  write "Result";
Chengsong
parents:
diff changeset
   821
  write minus2
Chengsong
parents:
diff changeset
   822
  """
Chengsong
parents:
diff changeset
   823
Chengsong
parents:
diff changeset
   824
  val prog3 = """
Chengsong
parents:
diff changeset
   825
  start := 1000;
Chengsong
parents:
diff changeset
   826
  x := start;
Chengsong
parents:
diff changeset
   827
  y := start;
Chengsong
parents:
diff changeset
   828
  z := start;
Chengsong
parents:
diff changeset
   829
  while 0 < x do {
Chengsong
parents:
diff changeset
   830
  while 0 < y do {
Chengsong
parents:
diff changeset
   831
    while 0 < z do {
Chengsong
parents:
diff changeset
   832
      z := z - 1
Chengsong
parents:
diff changeset
   833
    };
Chengsong
parents:
diff changeset
   834
    z := start;
Chengsong
parents:
diff changeset
   835
    y := y - 1
Chengsong
parents:
diff changeset
   836
  };     
Chengsong
parents:
diff changeset
   837
  y := start;
Chengsong
parents:
diff changeset
   838
  x := x - 1
Chengsong
parents:
diff changeset
   839
  }
Chengsong
parents:
diff changeset
   840
  """
Chengsong
parents:
diff changeset
   841
  /*
Chengsong
parents:
diff changeset
   842
  for(i <- 400 to 400 by 1){
Chengsong
parents:
diff changeset
   843
    println(i+":")
Chengsong
parents:
diff changeset
   844
    blexing_simp(WHILE_REGS, prog2 * i)
Chengsong
parents:
diff changeset
   845
  } */
Chengsong
parents:
diff changeset
   846
Chengsong
parents:
diff changeset
   847
    /*
Chengsong
parents:
diff changeset
   848
    for (i <- 2 to 5){
Chengsong
parents:
diff changeset
   849
      for(j <- 1 to 3){
Chengsong
parents:
diff changeset
   850
        println(i,j)
Chengsong
parents:
diff changeset
   851
        small_de = i
Chengsong
parents:
diff changeset
   852
        usual_de = i + j
Chengsong
parents:
diff changeset
   853
        big_de = i + 2*j 
Chengsong
parents:
diff changeset
   854
        blexing_simp(AWHILE_REGS, prog2 * 100)
Chengsong
parents:
diff changeset
   855
      }
Chengsong
parents:
diff changeset
   856
    }*/
Chengsong
parents:
diff changeset
   857
Chengsong
parents:
diff changeset
   858
  /*
Chengsong
parents:
diff changeset
   859
  println("Tokens of prog2")
Chengsong
parents:
diff changeset
   860
  println(tokenise(WHILE_REGS, prog2).mkString("\n"))
Chengsong
parents:
diff changeset
   861
Chengsong
parents:
diff changeset
   862
  val fib_tokens = tokenise(WHILE_REGS, prog2)
Chengsong
parents:
diff changeset
   863
  fib_tokens.map{case (s1, s2) => (escape(s1), escape(s2))}.mkString(",\n")
Chengsong
parents:
diff changeset
   864
Chengsong
parents:
diff changeset
   865
Chengsong
parents:
diff changeset
   866
  val test_tokens = tokenise(WHILE_REGS, prog3)
Chengsong
parents:
diff changeset
   867
  test_tokens.map{case (s1, s2) => (escape(s1), escape(s2))}.mkString(",\n")
Chengsong
parents:
diff changeset
   868
  */
Chengsong
parents:
diff changeset
   869
Chengsong
parents:
diff changeset
   870
  /*
Chengsong
parents:
diff changeset
   871
  println("time test for blexing_simp")
Chengsong
parents:
diff changeset
   872
  for (i <- 1 to 1 by 1) {
Chengsong
parents:
diff changeset
   873
    lexing_simp(WHILE_REGS, prog2 * i)
Chengsong
parents:
diff changeset
   874
    blexing_simp(WHILE_REGS, prog2 * i)
Chengsong
parents:
diff changeset
   875
    for( j <- 0 to each_simp_timeb.length - 1){
Chengsong
parents:
diff changeset
   876
      if( each_simp_timeb(j)/each_simp_time(j) >= 10.0 )
Chengsong
parents:
diff changeset
   877
        println(j, each_simp_timeb(j), each_simp_time(j))
Chengsong
parents:
diff changeset
   878
    }
Chengsong
parents:
diff changeset
   879
  }
Chengsong
parents:
diff changeset
   880
  */
Chengsong
parents:
diff changeset
   881
Chengsong
parents:
diff changeset
   882
Chengsong
parents:
diff changeset
   883
  //--------------------------------------------------------------------------------------------------------END OF NON-BITCODE PART (TESTING)
Chengsong
parents:
diff changeset
   884
Chengsong
parents:
diff changeset
   885
Chengsong
parents:
diff changeset
   886
Chengsong
parents:
diff changeset
   887
  def clear() = {
Chengsong
parents:
diff changeset
   888
    print("")
Chengsong
parents:
diff changeset
   889
    //print("\33[H\33[2J")
Chengsong
parents:
diff changeset
   890
  }
Chengsong
parents:
diff changeset
   891
Chengsong
parents:
diff changeset
   892
  //testing the two lexings produce the same value
Chengsong
parents:
diff changeset
   893
  //enumerates strings of length n over alphabet cs
Chengsong
parents:
diff changeset
   894
  def strs(n: Int, cs: String) : Set[String] = {
Chengsong
parents:
diff changeset
   895
    if (n == 0) Set("")
Chengsong
parents:
diff changeset
   896
    else {
Chengsong
parents:
diff changeset
   897
      val ss = strs(n - 1, cs)
Chengsong
parents:
diff changeset
   898
      ss ++
Chengsong
parents:
diff changeset
   899
      (for (s <- ss; c <- cs.toList) yield c + s)
Chengsong
parents:
diff changeset
   900
    }
Chengsong
parents:
diff changeset
   901
  }
Chengsong
parents:
diff changeset
   902
  def enum(n: Int, s: String) : Stream[Rexp] = n match {
Chengsong
parents:
diff changeset
   903
    case 0 => ZERO #:: ONE #:: s.toStream.map(CHAR)
Chengsong
parents:
diff changeset
   904
    case n => {  
Chengsong
parents:
diff changeset
   905
      val rs = enum(n - 1, s)
Chengsong
parents:
diff changeset
   906
      rs #:::
Chengsong
parents:
diff changeset
   907
      (for (r1 <- rs; r2 <- rs) yield ALT(r1, r2)) #:::
Chengsong
parents:
diff changeset
   908
      (for (r1 <- rs; r2 <- rs) yield SEQ(r1, r2)) #:::
Chengsong
parents:
diff changeset
   909
      (for (r1 <- rs) yield STAR(r1))
Chengsong
parents:
diff changeset
   910
    }
Chengsong
parents:
diff changeset
   911
  }
Chengsong
parents:
diff changeset
   912
Chengsong
parents:
diff changeset
   913
  //tests blexing and lexing
Chengsong
parents:
diff changeset
   914
  def tests_blexer_simp(ss: Set[String])(r: Rexp) = {
Chengsong
parents:
diff changeset
   915
    clear()
Chengsong
parents:
diff changeset
   916
    //println(s"Testing ${r}")
Chengsong
parents:
diff changeset
   917
    for (s <- ss.par) yield {
Chengsong
parents:
diff changeset
   918
      val res1 = Try(Some(lexing_simp(r, s))).getOrElse(None)
5
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   919
      val res2 = Try(Some(super_blexing_simp(r, s))).getOrElse(None)
0
Chengsong
parents:
diff changeset
   920
      if (res1 != res2) println(s"Disagree on ${r} and ${s}")
Chengsong
parents:
diff changeset
   921
      if (res1 != res2) println(s"   ${res1} !=  ${res2}")
Chengsong
parents:
diff changeset
   922
      if (res1 != res2) Some((r, s)) else None
Chengsong
parents:
diff changeset
   923
    }
Chengsong
parents:
diff changeset
   924
  }
Chengsong
parents:
diff changeset
   925
Chengsong
parents:
diff changeset
   926
Chengsong
parents:
diff changeset
   927
5
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   928
  
0
Chengsong
parents:
diff changeset
   929
  /*
Chengsong
parents:
diff changeset
   930
  def single_expression_explorer(ar: ARexp, ss: Set[String]): Unit = {
Chengsong
parents:
diff changeset
   931
    for (s <- ss){
Chengsong
parents:
diff changeset
   932
      
Chengsong
parents:
diff changeset
   933
      val der_res = bder(c, ar) 
Chengsong
parents:
diff changeset
   934
      val simp_res = bsimp(der_res)
Chengsong
parents:
diff changeset
   935
      println(asize(der_res))
Chengsong
parents:
diff changeset
   936
      println(asize(simp_res))
Chengsong
parents:
diff changeset
   937
      single_expression_explorer(simp_res, (sc - c))
Chengsong
parents:
diff changeset
   938
    }
Chengsong
parents:
diff changeset
   939
  }*/
Chengsong
parents:
diff changeset
   940
Chengsong
parents:
diff changeset
   941
  //single_expression_explorer(internalise(("c"~("a"+"b"))%) , Set('a','b','c'))
Chengsong
parents:
diff changeset
   942
Chengsong
parents:
diff changeset
   943
Chengsong
parents:
diff changeset
   944
}
Chengsong
parents:
diff changeset
   945
Chengsong
parents:
diff changeset
   946
import Rexp.Bits
Chengsong
parents:
diff changeset
   947
abstract class ARexp 
Chengsong
parents:
diff changeset
   948
case object AZERO extends ARexp
Chengsong
parents:
diff changeset
   949
case class AONE(bs: Bits) extends ARexp
Chengsong
parents:
diff changeset
   950
case class ACHAR(bs: Bits, f: Char) extends ARexp
Chengsong
parents:
diff changeset
   951
case class AALTS(bs: Bits, rs: List[ARexp]) extends ARexp 
Chengsong
parents:
diff changeset
   952
case class ASEQ(bs: Bits, r1: ARexp, r2: ARexp) extends ARexp 
Chengsong
parents:
diff changeset
   953
case class ASTAR(bs: Bits, r: ARexp) extends ARexp 
Chengsong
parents:
diff changeset
   954
Chengsong
parents:
diff changeset
   955
Chengsong
parents:
diff changeset
   956
Chengsong
parents:
diff changeset
   957
abstract class Val
Chengsong
parents:
diff changeset
   958
case object Empty extends Val
Chengsong
parents:
diff changeset
   959
case class Chr(c: Char) extends Val
Chengsong
parents:
diff changeset
   960
case class Sequ(v1: Val, v2: Val) extends Val
Chengsong
parents:
diff changeset
   961
case class Left(v: Val) extends Val
Chengsong
parents:
diff changeset
   962
case class Right(v: Val) extends Val
Chengsong
parents:
diff changeset
   963
case class Stars(vs: List[Val]) extends Val
Chengsong
parents:
diff changeset
   964
case class Rec(x: String, v: Val) extends Val
17
Chengsong
parents: 16
diff changeset
   965
case object undefined extends Val
0
Chengsong
parents:
diff changeset
   966
//case class Pos(i: Int, v: Val) extends Val
Chengsong
parents:
diff changeset
   967
case object Prd extends Val