lex_blex_Frankensteined.scala
author Chengsong
Thu, 16 Apr 2020 09:14:15 +0100
changeset 149 6c5920fd02a7
parent 148 c8ef391dd6f7
child 150 b51d34113d47
permissions -rw-r--r--
before changes to bsimp2
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package RexpRelated
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import scala.language.implicitConversions    
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import scala.language.reflectiveCalls
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import scala.annotation.tailrec   
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import scala.util.Try
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abstract class Bit
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case object Z extends Bit
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case object S extends Bit
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//case class C(c: Char) extends Bit
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abstract class Rexp 
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case object ZERO extends Rexp
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case object ONE extends Rexp
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case class CHAR(c: Char) extends Rexp
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case class ALTS(rs: List[Rexp]) extends Rexp 
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case class SEQ(r1: Rexp, r2: Rexp) extends Rexp 
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case class STAR(r: Rexp) extends Rexp 
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case class RECD(x: String, r: Rexp) extends Rexp
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object Rexp{
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  type Bits = List[Bit]
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  // abbreviations
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  type Mon = (Char, Rexp)
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  type Lin = Set[Mon]
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  def ALT(r1: Rexp, r2: Rexp) = ALTS(List(r1, r2))
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  def PLUS(r: Rexp) = SEQ(r, STAR(r))
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  def AALT(bs: Bits, r1: ARexp, r2: ARexp) = AALTS(bs, List(r1, r2))
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  def distinctBy[B, C](xs: List[B], f: B => C, acc: List[C] = Nil): List[B] = xs match {
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    case Nil => Nil
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    case (x::xs) => {
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      val res = f(x)
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      if (acc.contains(res)) distinctBy(xs, f, acc)  
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      else x::distinctBy(xs, f, res::acc)
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    }
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  } 
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  // some convenience for typing in regular expressions
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  def charlist2rexp(s : List[Char]): Rexp = s match {
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    case Nil => ONE
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    case c::Nil => CHAR(c)
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    case c::s => SEQ(CHAR(c), charlist2rexp(s))
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  }
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  implicit def string2rexp(s : String) : Rexp = charlist2rexp(s.toList)
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  implicit def RexpOps(r: Rexp) = new {
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    def | (s: Rexp) = ALT(r, s)
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    def % = STAR(r)
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    def ~ (s: Rexp) = SEQ(r, s)
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  }
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  implicit def stringOps(s: String) = new {
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    def | (r: Rexp) = ALT(s, r)
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    def | (r: String) = ALT(s, r)
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    def % = STAR(s)
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    def ~ (r: Rexp) = SEQ(s, r)
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    def ~ (r: String) = SEQ(s, r)
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    def $ (r: Rexp) = RECD(s, r)
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  }
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  // translation into ARexps
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  def fuse(bs: Bits, r: ARexp) : ARexp = r match {
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    case AZERO => AZERO
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    case AONE(cs) => AONE(bs ++ cs)
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    case ACHAR(cs, f) => ACHAR(bs ++ cs, f)
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    case AALTS(cs, rs) => AALTS(bs ++ cs, rs)
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    case ASEQ(cs, r1, r2) => ASEQ(bs ++ cs, r1, r2)
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    case ASTAR(cs, r) => ASTAR(bs ++ cs, r)
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  }
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  def internalise(r: Rexp) : ARexp = r match {
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    case ZERO => AZERO
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    case ONE => AONE(Nil)
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    case CHAR(c) => ACHAR(Nil, c)
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    case ALTS(List(r1, r2)) => 
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      AALTS(Nil, List(fuse(List(Z), internalise(r1)), fuse(List(S), internalise(r2))))
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    case ALTS(r1::rs) => {
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      val AALTS(Nil, rs2) = internalise(ALTS(rs))
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      AALTS(Nil, fuse(List(Z), internalise(r1)) :: rs2.map(fuse(List(S), _)))
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    }
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    case SEQ(r1, r2) => ASEQ(Nil, internalise(r1), internalise(r2))
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    case STAR(r) => ASTAR(Nil, internalise(r))
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    case RECD(x, r) => internalise(r)
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  }
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  internalise(("a" | "ab") ~ ("b" | ""))
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  def decode_aux(r: Rexp, bs: Bits) : (Val, Bits) = (r, bs) match {
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    case (ONE, bs) => (Empty, bs)
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    case (CHAR(f), bs) => (Chr(f), bs)
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    case (ALTS(r::Nil), bs) => decode_aux(r, bs)//this case seems only used when we simp a regex before derivatives and it contains things like alt("a")
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    case (ALTS(rs), bs) => bs match {
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      case Z::bs1 => {
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        val (v, bs2) = decode_aux(rs.head, bs1)
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        (Left(v), bs2)
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      }
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      case S::bs1 => {
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        val (v, bs2) = decode_aux(ALTS(rs.tail), bs1)
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        (Right(v), bs2)			
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      }
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    }
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    case (SEQ(r1, r2), bs) => {
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      val (v1, bs1) = decode_aux(r1, bs)
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      val (v2, bs2) = decode_aux(r2, bs1)
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      (Sequ(v1, v2), bs2)
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    }
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    case (STAR(r1), S::bs) => {
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      val (v, bs1) = decode_aux(r1, bs)
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      //println(v)
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      val (Stars(vs), bs2) = decode_aux(STAR(r1), bs1)
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      (Stars(v::vs), bs2)
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    }
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    case (STAR(_), Z::bs) => (Stars(Nil), bs)
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    case (RECD(x, r1), bs) => {
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      val (v, bs1) = decode_aux(r1, bs)
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      (Rec(x, v), bs1)
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    }
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    case (r, Nil) => (Stars(Nil), Nil)
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  }
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  def decode(r: Rexp, bs: Bits) = decode_aux(r, bs) match {
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    case (v, Nil) => v
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    case _ => throw new Exception("Not decodable")
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  }
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  def code(v: Val): Bits = v match {
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    case Empty => Nil
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    case Chr(a) => Nil
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    case Left(v) => Z :: code(v)
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    case Right(v) => S :: code(v)
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    case Sequ(v1, v2) => code(v1) ::: code(v2)
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    case Stars(Nil) => Z::Nil
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    case Stars(v::vs) => S::code(v) ::: code(Stars(vs))
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  }
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  //note that left and right are not recorded
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  //although they guide the retrival
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  //in contrast with stars 
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  def retrieve(r: ARexp, v: Val): Bits = (r,v) match {
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    case (AONE(bs), Empty) => bs
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    case (ACHAR(bs, c), Chr(d)) => bs
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    case (AALTS(bs, a::Nil), v) => bs ++ retrieve(a, v)
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    case (AALTS(bs, as), Left(v)) => bs ++ retrieve(as.head,v)
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    case (AALTS(bs, as), Right(v)) => bs ++ retrieve(AALTS(Nil,as.tail),v)
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    case (ASEQ(bs, a1, a2), Sequ(v1, v2)) => bs ++ retrieve(a1, v1) ++ retrieve(a2, v2)
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    case (ASTAR(bs, a), Stars(Nil)) => bs ++ List(Z) 
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    case (ASTAR(bs, a), Stars(v::vs)) => bs ++ List(S) ++ retrieve(a, v) ++ retrieve(ASTAR(Nil, a), Stars(vs))
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  }//bug here last clause should not add list(S)
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  //erase function: extracts the regx from Aregex
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  def erase(r:ARexp): Rexp = r match{
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    case AZERO => ZERO
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    case AONE(_) => ONE
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    case ACHAR(bs, f) => CHAR(f)
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    case AALTS(bs, rs) => ALTS(rs.map(erase(_)))
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    case ASEQ(bs, r1, r2) => SEQ (erase(r1), erase(r2))
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    case ASTAR(cs, r)=> STAR(erase(r))
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  }
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  //--------------------------------------------------------------------------------------------------------START OF NON-BITCODE PART
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  // nullable function: tests whether the regular 
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  // expression can recognise the empty string
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  def nullable (r: Rexp) : Boolean = r match {
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    case ZERO => false
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    case ONE => true
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    case CHAR(_) => false
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    case ALTS(rs) => rs.exists(nullable)
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    case SEQ(r1, r2) => nullable(r1) && nullable(r2)
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    case STAR(_) => true
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    case RECD(_, r) => nullable(r)
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    //case PLUS(r) => nullable(r)
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  }
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  // derivative of a regular expression w.r.t. a character
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  def der (c: Char, r: Rexp) : Rexp = r match {
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    case ZERO => ZERO
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    case ONE => ZERO
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    case CHAR(f) => if (c == f) ONE else ZERO
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    case ALTS(List(r1, r2)) => ALTS(List(der(c, r1), der(c, r2)))
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    case SEQ(r1, r2) => 
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      if (nullable(r1)) ALTS(List(SEQ(der(c, r1), r2), der(c, r2)))
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      else SEQ(der(c, r1), r2)
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    case STAR(r) => SEQ(der(c, r), STAR(r))
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    case RECD(_, r1) => der(c, r1)
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    //case PLUS(r) => SEQ(der(c, r), STAR(r))
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  }
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  def ders (s: List[Char], r: Rexp) : Rexp = s match {
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    case Nil => r
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    case c::s => ders(s, der(c, r))
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  }
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def der_seqo(r:Rexp, s: List[Char],acc: List[Rexp]) : List[Rexp] = s match{
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    case Nil => acc ::: List(r)
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    case c::cs => der_seqo(der(c, r), cs, acc ::: List(r))
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  }
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  def der_seq_revo(r:Rexp, s: List[Char], acc: List[Rexp]): List[Rexp] = s match{
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    case Nil => r::acc
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    case c::cs =>der_seq_revo(r, cs, ders(s, r) :: acc  )
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  }
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  def re_closeo(l1: List[Rexp], l2: List[Rexp], re_init: Rexp): Rexp = l1 match {
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    case Nil => re_init
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    case c::cs => if(nullable(c)) re_closeo(cs, l2.tail, ALT(re_init,  l2.head)  ) 
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    else re_closeo(cs, l2.tail, re_init)
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  }
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  //HERE
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  def closed_string_dero(r1: Rexp, r2: Rexp, s: List[Char]): Rexp = {
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    val l1 = der_seqo(r1, s, Nil)
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    val l2 = der_seq_revo(r2, s, Nil)
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    val Re = re_closeo((l1.reverse).tail, l2.tail, SEQ(l1.last, l2.head))
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    Re
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  }
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  //derivative w.r.t string
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def ders2(s: List[Char], r: Rexp) : Rexp = (s, r) match {
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  case (Nil, r) => r
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  case (s, ZERO) => ZERO
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  case (s, ONE) => if (s == Nil) ONE else ZERO
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  case (s, CHAR(c)) => if (s == List(c)) ONE else 
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                       if (s == Nil) CHAR(c) else ZERO
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  case (s, ALTS(List(r1, r2))) => ALT(ders2(s, r1), ders2(s, r2))
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  case (s, SEQ(r1, r2)) => closed_string_dero(r1, r2, s)
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  case (c::cs, STAR(r)) => closed_string_dero(der(c, r), STAR(r), cs)
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}
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0
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  def flatten(v: Val) : String = v match {
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    case Empty => ""
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    case Chr(c) => c.toString
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    case Left(v) => flatten(v)
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    case Right(v) => flatten(v)
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    case Sequ(v1, v2) => flatten(v1) + flatten(v2)
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    case Stars(vs) => vs.map(flatten).mkString
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    case Rec(_, v) => flatten(v)
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  }
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  // extracts an environment from a value
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  def env(v: Val) : List[(String, String)] = v match {
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    case Empty => Nil
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    case Chr(c) => Nil
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    case Left(v) => env(v)
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    case Right(v) => env(v)
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    case Sequ(v1, v2) => env(v1) ::: env(v2)
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    case Stars(vs) => vs.flatMap(env)
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    case Rec(x, v) => (x, flatten(v))::env(v)
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  }
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  // injection part
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  def mkeps(r: Rexp) : Val = r match {
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    case ONE => Empty
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    case ALTS(List(r1, r2)) => 
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      if (nullable(r1)) Left(mkeps(r1)) else Right(mkeps(r2))
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    case SEQ(r1, r2) => Sequ(mkeps(r1), mkeps(r2))
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    case STAR(r) => Stars(Nil)
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    case RECD(x, r) => Rec(x, mkeps(r))
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    //case PLUS(r) => Stars(List(mkeps(r)))
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  }
148
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  def haschr(r: Rexp) : Boolean = r match {
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    case CHAR(c) => true
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    case STAR(r0) => haschr(r0)
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    case SEQ(r1, r2) => haschr(r1) && nullable(r2) || haschr(r2) && nullable(r1)
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    case ALTS(List(r1, r2)) => haschr(r1) || haschr(r2)
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    case ONE => false
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    case ZERO => false
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  }
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  def haschar(r: Rexp, c: Char) : Boolean = r match {
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    case CHAR(d) => if(c == d) true else false
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    case SEQ(r1, r2) => if(haschar(r1, c) && nullable(r2)) true else if(haschar(r2, c) && nullable(r1) ) true else false
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    case STAR(r) => if(haschar(r, c)) true else false
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    case ALTS(List(r1, r2)) => if(haschar(r1, c) || haschar(r2, c)) true else false
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    case ONE => false
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    case ZERO => false 
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  }
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  def mkchr(r: Rexp) : Val = r match {
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    case SEQ(r1, r2) => 
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      if(haschr(r1) && nullable(r2)) Sequ(mkchr(r1), mkeps(r2)) 
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      else if(nullable(r1) && haschr(r2)) Sequ(mkeps(r1), mkchr(r2))
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      else throw new Exception(r.toString)
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    case ALTS(List(r1, r2)) => if (haschr(r1)) Left(mkchr(r1)) else Right(mkchr(r2))
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    case STAR(r0) => Stars(List(mkchr(r0)))
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    case CHAR(c) => Chr(c)
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    case _ => throw new Exception("the regex you gave me can't make a char")
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  }
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  def mkchar(r: Rexp, c: Char) : Val = r match {
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    case CHAR(d) => Chr(c)//if(c == d)  Chr(c) else error
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    case ALTS(List(r1, r2)) =>
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      if (haschar(r1, c)) Left(mkchar(r1, c)) else Right(mkchar(r2, c))
0
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148
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    case SEQ(r1, r2) => {if(haschar(r1, c)) Sequ(mkchar(r1, c), mkeps(r2)) else Sequ(mkeps(r1), mkchar(r2, c))}
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    case STAR(r) =>Stars(List(mkchar(r, c)))
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   294
  }
0
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  def inj(r: Rexp, c: Char, v: Val) : Val = (r, v) match {
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   296
    case (STAR(r), Sequ(v1, Stars(vs))) => Stars(inj(r, c, v1)::vs)
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   297
    case (SEQ(r1, r2), Sequ(v1, v2)) => Sequ(inj(r1, c, v1), v2)
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   298
    case (SEQ(r1, r2), Left(Sequ(v1, v2))) => Sequ(inj(r1, c, v1), v2)
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   299
    case (SEQ(r1, r2), Right(v2)) => Sequ(mkeps(r1), inj(r2, c, v2))
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    case (ALTS(List(r1, r2)), Left(v1)) => Left(inj(r1, c, v1))
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    case (ALTS(List(r1, r2)), Right(v2)) => Right(inj(r2, c, v2))
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    case (CHAR(_), Empty) => Chr(c) 
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    case (RECD(x, r1), _) => Rec(x, inj(r1, c, v))
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    //case (PLUS(r), Sequ(v1, Stars(vs))) => Stars(inj(r, c, v1)::vs)
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  }
148
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  def fuzzy_inj(r: ARexp, c: Char, v: Val) : Val = v match {
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   307
    case Stars(vs) => r match {//vs
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      case ASTAR(bs, r0) => inj(     erase(r), c, Sequ(mkeps(erase(bder(c, r0))), v)     )
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      case ASEQ(bs, r1, r2) => inj(erase(r), c, Sequ(mkeps(erase(bder(c, r1))), v) )
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   310
    }
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   311
    case Sequ(v1, v2) => r match {
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      case ASTAR(bs, r0) => inj(erase(r), c, Sequ(mkchar(erase(bder(c, r0)), c), v2))
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   313
      case _ => v
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   314
    }
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   315
    case _ => v
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   316
  }
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   317
  /*def gen_rect(r: Rexp) : Val => Val = {
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   318
    //lingqi
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   319
    //buyao sanle 
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   320
    val r1 = bsimp(r)
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   321
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   322
  }
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   323
  def fuzzy_inj(r: ARexp, c: Char, v: Val) : Val = {
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   324
    val f = gen_rect(r)
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   325
    val vo = f(v)
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   326
    inj(r, c, vo)
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   327
  }*/
0
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   328
  def lex(r: Rexp, s: List[Char]) : Val = s match {
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   329
    case Nil => if (nullable(r)) mkeps(r) else throw new Exception("Not matched")
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   330
    case c::cs => inj(r, c, lex(der(c, r), cs))
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diff changeset
   331
  }
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   332
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   333
  def lexing(r: Rexp, s: String) : Val = lex(r, s.toList)
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   334
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   335
  // some "rectification" functions for simplification
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   336
  def F_ID(v: Val): Val = v
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   337
  def F_RIGHT(f: Val => Val) = (v:Val) => Right(f(v))
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   338
  def F_LEFT(f: Val => Val) = (v:Val) => Left(f(v))
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   339
  def F_ALT(f1: Val => Val, f2: Val => Val) = (v:Val) => v match {
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   340
    case Right(v) => Right(f2(v))
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   341
    case Left(v) => Left(f1(v))
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diff changeset
   342
  }
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   343
  def F_SEQ(f1: Val => Val, f2: Val => Val) = (v:Val) => v match {
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   344
    case Sequ(v1, v2) => Sequ(f1(v1), f2(v2))
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   345
  }
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   346
  def F_SEQ_Empty1(f1: Val => Val, f2: Val => Val) = 
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   347
    (v:Val) => Sequ(f1(Empty), f2(v))
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   348
  def F_SEQ_Empty2(f1: Val => Val, f2: Val => Val) = 
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   349
    (v:Val) => Sequ(f1(v), f2(Empty))
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   350
  def F_RECD(f: Val => Val) = (v:Val) => v match {
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   351
    case Rec(x, v) => Rec(x, f(v))
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diff changeset
   352
  }
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   353
  def F_ERROR(v: Val): Val = throw new Exception("error")
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   354
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   355
  // simplification of regular expressions returning also an
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   356
  // rectification function; no simplification under STAR 
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   357
  def simp(r: Rexp): (Rexp, Val => Val) = r match {
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   358
    case ALTS(List(r1, r2)) => {
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diff changeset
   359
      val (r1s, f1s) = simp(r1)
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diff changeset
   360
      val (r2s, f2s) = simp(r2)
Chengsong
parents:
diff changeset
   361
      (r1s, r2s) match {
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parents:
diff changeset
   362
        case (ZERO, _) => (r2s, F_RIGHT(f2s))
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parents:
diff changeset
   363
        case (_, ZERO) => (r1s, F_LEFT(f1s))
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parents:
diff changeset
   364
        case _ => if (r1s == r2s) (r1s, F_LEFT(f1s))
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diff changeset
   365
                  else (ALTS(List(r1s, r2s)), F_ALT(f1s, f2s)) 
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diff changeset
   366
      }
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diff changeset
   367
    }
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diff changeset
   368
    case SEQ(r1, r2) => {
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diff changeset
   369
      val (r1s, f1s) = simp(r1)
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diff changeset
   370
      val (r2s, f2s) = simp(r2)
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diff changeset
   371
      (r1s, r2s) match {
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   372
        case (ZERO, _) => (ZERO, F_ERROR)
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diff changeset
   373
        case (_, ZERO) => (ZERO, F_ERROR)
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diff changeset
   374
        case (ONE, _) => (r2s, F_SEQ_Empty1(f1s, f2s))
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parents:
diff changeset
   375
        case (_, ONE) => (r1s, F_SEQ_Empty2(f1s, f2s))
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   376
        case _ => (SEQ(r1s,r2s), F_SEQ(f1s, f2s))
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diff changeset
   377
      }
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diff changeset
   378
    }
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   379
    case RECD(x, r1) => {
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diff changeset
   380
      val (r1s, f1s) = simp(r1)
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diff changeset
   381
      (RECD(x, r1s), F_RECD(f1s))
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diff changeset
   382
    }
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   383
    case r => (r, F_ID)
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diff changeset
   384
  }
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   385
  /*
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   386
  val each_simp_time = scala.collection.mutable.ArrayBuffer.empty[Long]
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   387
  val each_simp_timeb = scala.collection.mutable.ArrayBuffer.empty[Long]
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   388
  */
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   389
  def lex_simp(r: Rexp, s: List[Char]) : Val = s match {
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   390
    case Nil => {
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diff changeset
   391
      if (nullable(r)) {
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diff changeset
   392
        mkeps(r) 
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diff changeset
   393
      }
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diff changeset
   394
      else throw new Exception("Not matched")
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parents:
diff changeset
   395
    }
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parents:
diff changeset
   396
    case c::cs => {
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parents:
diff changeset
   397
      val (r_simp, f_simp) = simp(der(c, r))
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parents:
diff changeset
   398
      inj(r, c, f_simp(lex_simp(r_simp, cs)))
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parents:
diff changeset
   399
    }
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parents:
diff changeset
   400
  }
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parents:
diff changeset
   401
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parents:
diff changeset
   402
  def lexing_simp(r: Rexp, s: String) : Val = lex_simp(r, s.toList)
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parents:
diff changeset
   403
Chengsong
parents:
diff changeset
   404
  //println(lexing_simp(("a" | "ab") ~ ("b" | ""), "ab"))
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parents:
diff changeset
   405
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parents:
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   406
  // filters out all white spaces
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parents:
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   407
  def tokenise(r: Rexp, s: String) = 
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parents:
diff changeset
   408
    env(lexing_simp(r, s)).filterNot { _._1 == "w"}
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parents:
diff changeset
   409
Chengsong
parents:
diff changeset
   410
Chengsong
parents:
diff changeset
   411
  //reads the string from a file 
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parents:
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   412
  def fromFile(name: String) : String = 
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parents:
diff changeset
   413
    io.Source.fromFile(name).mkString
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parents:
diff changeset
   414
Chengsong
parents:
diff changeset
   415
  def tokenise_file(r: Rexp, name: String) = 
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parents:
diff changeset
   416
    tokenise(r, fromFile(name))
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diff changeset
   417
  
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parents:
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   418
  //   Testing
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parents:
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   419
  //============
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parents:
diff changeset
   420
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parents:
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   421
  def time[T](code: => T) = {
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parents:
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   422
    val start = System.nanoTime()
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parents:
diff changeset
   423
    val result = code
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parents:
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   424
    val end = System.nanoTime()
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parents:
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   425
    println((end - start)/1.0e9)
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parents:
diff changeset
   426
    result
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parents:
diff changeset
   427
  }
Chengsong
parents:
diff changeset
   428
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parents:
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   429
  //--------------------------------------------------------------------------------------------------------END OF NON-BITCODE PART
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parents:
diff changeset
   430
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parents:
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   431
  // bnullable function: tests whether the aregular 
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   432
  // expression can recognise the empty string
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parents:
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   433
  def bnullable (r: ARexp) : Boolean = r match {
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diff changeset
   434
    case AZERO => false
Chengsong
parents:
diff changeset
   435
    case AONE(_) => true
Chengsong
parents:
diff changeset
   436
    case ACHAR(_,_) => false
Chengsong
parents:
diff changeset
   437
    case AALTS(_, rs) => rs.exists(bnullable)
Chengsong
parents:
diff changeset
   438
    case ASEQ(_, r1, r2) => bnullable(r1) && bnullable(r2)
Chengsong
parents:
diff changeset
   439
    case ASTAR(_, _) => true
Chengsong
parents:
diff changeset
   440
  }
Chengsong
parents:
diff changeset
   441
Chengsong
parents:
diff changeset
   442
  def mkepsBC(r: ARexp) : Bits = r match {
Chengsong
parents:
diff changeset
   443
    case AONE(bs) => bs
Chengsong
parents:
diff changeset
   444
    case AALTS(bs, rs) => {
Chengsong
parents:
diff changeset
   445
      val n = rs.indexWhere(bnullable)
Chengsong
parents:
diff changeset
   446
      bs ++ mkepsBC(rs(n))
Chengsong
parents:
diff changeset
   447
    }
Chengsong
parents:
diff changeset
   448
    case ASEQ(bs, r1, r2) => bs ++ mkepsBC(r1) ++ mkepsBC(r2)
Chengsong
parents:
diff changeset
   449
    case ASTAR(bs, r) => bs ++ List(Z)
Chengsong
parents:
diff changeset
   450
  }
Chengsong
parents:
diff changeset
   451
Chengsong
parents:
diff changeset
   452
  // derivative of a regular expression w.r.t. a character
Chengsong
parents:
diff changeset
   453
  def bder(c: Char, r: ARexp) : ARexp = r match {
Chengsong
parents:
diff changeset
   454
    case AZERO => AZERO
Chengsong
parents:
diff changeset
   455
    case AONE(_) => AZERO
12
768b833d6230 removed C(c) The retrieve and code in the previous version is still not correct and will crash. no prob now.
Chengsong
parents: 11
diff changeset
   456
    case ACHAR(bs, f) => if (c == f) AONE(bs) else AZERO
0
Chengsong
parents:
diff changeset
   457
    case AALTS(bs, rs) => AALTS(bs, rs.map(bder(c, _)))
Chengsong
parents:
diff changeset
   458
    case ASEQ(bs, r1, r2) => 
Chengsong
parents:
diff changeset
   459
      if (bnullable(r1)) AALT(bs, ASEQ(Nil, bder(c, r1), r2), fuse(mkepsBC(r1), bder(c, r2)))
Chengsong
parents:
diff changeset
   460
      else ASEQ(bs, bder(c, r1), r2)
Chengsong
parents:
diff changeset
   461
    case ASTAR(bs, r) => ASEQ(bs, fuse(List(S), bder(c, r)), ASTAR(Nil, r))
Chengsong
parents:
diff changeset
   462
  }
107
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   463
  def bder_rf(c: Char, r: ARexp) : ARexp = r match {
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   464
    case AZERO => AZERO
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   465
    case AONE(_) => AZERO
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   466
    case ACHAR(bs, f) => if (c == f) AONE(bs) else AZERO
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   467
    case AALTS(bs, rs) => AALTS(bs, rs.map(bder_rf(c, _)))
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   468
    case ASEQ(bs, r1, r2) =>
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   469
      if (bnullable(r1)) AALT(bs, ASEQ(Nil, bder_rf(c, r1), r2), fuse(mkepsBC(r1), bder_rf(c, r2)))
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   470
      else ASEQ(bs, bder_rf(c, r1), r2)
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   471
    case ASTAR(bs, r) => ASEQ(bs, fuse(List(S), bder_rf(c, r)), ASTAR(Nil, r))
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   472
  }
0
Chengsong
parents:
diff changeset
   473
  // derivative w.r.t. a string (iterates bder)
Chengsong
parents:
diff changeset
   474
  @tailrec
Chengsong
parents:
diff changeset
   475
  def bders (s: List[Char], r: ARexp) : ARexp = s match {
Chengsong
parents:
diff changeset
   476
    case Nil => r
Chengsong
parents:
diff changeset
   477
    case c::s => bders(s, bder(c, r))
Chengsong
parents:
diff changeset
   478
  }
107
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   479
  
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   480
  def bders_rf(s: List[Char], r: ARexp) : ARexp = s match {
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   481
    case Nil => r
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   482
    case c::s => bders_rf(s, bder_rf(c, r))
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   483
  }
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   484
  def all_zero_except_alt(rs: List[ARexp], a: ARexp): ARexp = rs match{
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   485
    case Nil => a
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   486
    case AZERO :: rs1 => all_zero_except_alt(rs1, a)
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   487
    case AALTS(bs, rs1) :: rs2 => {
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   488
      if (a == AZERO)
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   489
        all_zero_except_alt(rs2, AALTS(bs, rs1))
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   490
      else
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   491
        AZERO
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   492
    }
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   493
    case r1 :: rs2 => AZERO
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   494
  }
0
Chengsong
parents:
diff changeset
   495
  def flats(rs: List[ARexp]): List[ARexp] = rs match {
Chengsong
parents:
diff changeset
   496
      case Nil => Nil
Chengsong
parents:
diff changeset
   497
      case AZERO :: rs1 => flats(rs1)
Chengsong
parents:
diff changeset
   498
      case AALTS(bs, rs1) :: rs2 => rs1.map(fuse(bs, _)) ::: flats(rs2)
Chengsong
parents:
diff changeset
   499
      case r1 :: rs2 => r1 :: flats(rs2)
15
Chengsong
parents: 14
diff changeset
   500
  }
17
Chengsong
parents: 16
diff changeset
   501
  /*
15
Chengsong
parents: 14
diff changeset
   502
  def remove(v: Val): Val = v match{
Chengsong
parents: 14
diff changeset
   503
    case Right(v1) => v1
Chengsong
parents: 14
diff changeset
   504
    case Left(v1) => v1
Chengsong
parents: 14
diff changeset
   505
    case _ => throw new Exception("Not removable")
17
Chengsong
parents: 16
diff changeset
   506
  }*/
15
Chengsong
parents: 14
diff changeset
   507
  def augment(v: Val, i: Int): Val = if(i > 1) augment(Right(v), i - 1) else Right(v)
Chengsong
parents: 14
diff changeset
   508
//an overly complex version
Chengsong
parents: 14
diff changeset
   509
/*
Chengsong
parents: 14
diff changeset
   510
    if(rel_dist >0){//the regex we are dealing with is not what v points at
Chengsong
parents: 14
diff changeset
   511
      rs match{
Chengsong
parents: 14
diff changeset
   512
        case Nil => throw new Exception("Trying to simplify a non-existent value")
148
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   513
        case AZERO :: rs1 => right_shift(rs1, rel_dist - 1, remove(v))
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   514
        case AALTS(bs, rs1) :: rs2 => right_shift(rs2, rel_dist - 1, augment(v, rs1.length - 1))//rs1 is guaranteed to have a len geq 2
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   515
        case r1 :: rs2 => right_shift(rs2, rel_dist - 1, v)
15
Chengsong
parents: 14
diff changeset
   516
      }
0
Chengsong
parents:
diff changeset
   517
    }
15
Chengsong
parents: 14
diff changeset
   518
    else if(rel_dist == 0){//we are dealing with regex v is pointing to -- "v->r itself"
Chengsong
parents: 14
diff changeset
   519
      rs match{//r1 cannot be zero
148
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   520
        AALTS(bs, rs1) :: rs2 => right_shift(  )
15
Chengsong
parents: 14
diff changeset
   521
        AZERO::rs2 => throw new Exception("Value corresponds to zero")
148
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   522
        r1::rs2 => right_shift(rs2, rel_dist - 1, v)
15
Chengsong
parents: 14
diff changeset
   523
      }
Chengsong
parents: 14
diff changeset
   524
Chengsong
parents: 14
diff changeset
   525
    }
Chengsong
parents: 14
diff changeset
   526
    else{
Chengsong
parents: 14
diff changeset
   527
Chengsong
parents: 14
diff changeset
   528
    }
Chengsong
parents: 14
diff changeset
   529
    */
148
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   530
  //gives how much the regex at i has shifted right after flatten(on a list of simplified regexes)
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   531
  def right_shift(rs: List[ARexp], i: Int): Int = (rs, i) match {
15
Chengsong
parents: 14
diff changeset
   532
    case (_, 0) => 0
Chengsong
parents: 14
diff changeset
   533
    case (Nil, _) => 0
148
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   534
    case (AZERO :: rs1, _) => right_shift(rs1, i - 1) - 1
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   535
    case (AALTS(bs, rs1) :: rs2, _) => rs1.length - 1 + right_shift(rs2, i - 1)
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   536
    case (r1 :: rs2, _) => right_shift(rs2, i - 1)
15
Chengsong
parents: 14
diff changeset
   537
  }
0
Chengsong
parents:
diff changeset
   538
  def rflats(rs: List[Rexp]): List[Rexp] = rs match {
Chengsong
parents:
diff changeset
   539
    case Nil => Nil
Chengsong
parents:
diff changeset
   540
    case ZERO :: rs1 => rflats(rs1)
Chengsong
parents:
diff changeset
   541
    case ALTS(rs1) :: rs2 => rs1 ::: rflats(rs2)
Chengsong
parents:
diff changeset
   542
    case r1 :: rs2 => r1 :: rflats(rs2)
Chengsong
parents:
diff changeset
   543
  }
Chengsong
parents:
diff changeset
   544
  var flats_time = 0L
Chengsong
parents:
diff changeset
   545
  var dist_time = 0L
Chengsong
parents:
diff changeset
   546
  
Chengsong
parents:
diff changeset
   547
  def bsimp(r: ARexp): ARexp = r match {
Chengsong
parents:
diff changeset
   548
    case ASEQ(bs1, r1, r2) => (bsimp(r1), bsimp(r2)) match {
Chengsong
parents:
diff changeset
   549
        case (AZERO, _) => AZERO
Chengsong
parents:
diff changeset
   550
        case (_, AZERO) => AZERO
Chengsong
parents:
diff changeset
   551
        case (AONE(bs2), r2s) => fuse(bs1 ++ bs2, r2s)
Chengsong
parents:
diff changeset
   552
        case (r1s, r2s) => ASEQ(bs1, r1s, r2s)
Chengsong
parents:
diff changeset
   553
    }
Chengsong
parents:
diff changeset
   554
    case AALTS(bs1, rs) => {
Chengsong
parents:
diff changeset
   555
      val rs_simp = rs.map(bsimp)
Chengsong
parents:
diff changeset
   556
      val flat_res = flats(rs_simp)
Chengsong
parents:
diff changeset
   557
      val dist_res = distinctBy(flat_res, erase)
Chengsong
parents:
diff changeset
   558
      dist_res match {
Chengsong
parents:
diff changeset
   559
        case Nil => AZERO
93
Chengsong
parents: 92
diff changeset
   560
        case r :: Nil => fuse(bs1, r)
0
Chengsong
parents:
diff changeset
   561
        case rs => AALTS(bs1, rs)  
Chengsong
parents:
diff changeset
   562
      }
Chengsong
parents:
diff changeset
   563
    }
5
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   564
    //case ASTAR(bs, r) => ASTAR(bs, bsimp(r))
0
Chengsong
parents:
diff changeset
   565
    case r => r
Chengsong
parents:
diff changeset
   566
  }
107
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   567
  //minimise fuse operation if possible
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   568
  def bsimp_rf(r: ARexp):ARexp = r match {
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   569
     case ASEQ(bs1, r1, r2) => (bsimp_rf(r1), bsimp_rf(r2)) match {
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   570
        case (AZERO, _) => AZERO
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   571
        case (_, AZERO) => AZERO
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   572
        case (AONE(bs2), r2s) => fuse(bs1 ++ bs2, r2s)
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   573
        case (r1s, r2s) => ASEQ(bs1, r1s, r2s)
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   574
    }
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   575
    case AALTS(bs1, rs) => {
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   576
      //after map simp, before flats, check if all others simplify to 0s, if yes, do not fuse
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   577
      val rs_simp = rs.map(bsimp_rf)
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   578
      //prevent fuse from happening
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   579
      val fuse_alts = all_zero_except_alt(rs_simp, AZERO)//returns AZERO if not the case, return AALTS if yes
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   580
      if(fuse_alts == AZERO){
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   581
        val flat_res = flats(rs_simp)
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   582
        val dist_res = distinctBy(flat_res, erase)
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   583
        dist_res match {
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   584
          case Nil => AZERO
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   585
          case r :: Nil => fuse(bs1, r)
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   586
          case rs => AALTS(bs1, rs)  
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   587
        }
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   588
      }
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   589
      else{
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   590
        fuse(bs1, fuse_alts)
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   591
      }
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   592
    }
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   593
    //case ASTAR(bs, r) => ASTAR(bs, bsimp(r))
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   594
    case r => r   
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   595
  }
93
Chengsong
parents: 92
diff changeset
   596
  //only print at the top level
Chengsong
parents: 92
diff changeset
   597
148
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   598
  //find_pos returns the index of a certain regex in a list of regex
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   599
  //the leftmost regex is given the index 0 and the regex next to it
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   600
  //is given 1 and so on 
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   601
  //it needs the value to point out which regex it wants to get index of
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   602
  //find_pos_aux does essentially the same thing as find_pos, except that
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   603
  //it receives an alts instead of a list of regular expressions
17
Chengsong
parents: 16
diff changeset
   604
  def find_pos(v: Val, rs: List[ARexp]): Int = (v, rs) match{
Chengsong
parents: 16
diff changeset
   605
    case (v, r::Nil) => 0
15
Chengsong
parents: 14
diff changeset
   606
    case (Right(v), r::rs) => find_pos(v, rs) + 1
17
Chengsong
parents: 16
diff changeset
   607
    case (Left(v), r::rs) => 0
Chengsong
parents: 16
diff changeset
   608
    //case (v, _) => 0
Chengsong
parents: 16
diff changeset
   609
  }
Chengsong
parents: 16
diff changeset
   610
  def find_pos_aux(v: Val, r: ARexp): Int = r match {
Chengsong
parents: 16
diff changeset
   611
    case AALTS(bs, rs) => find_pos(v, rs)
Chengsong
parents: 16
diff changeset
   612
    case r => 0
15
Chengsong
parents: 14
diff changeset
   613
  }
17
Chengsong
parents: 16
diff changeset
   614
  def remove(v: Val, rs: List[ARexp]) : Val = (v,rs) match {//remove the outmost layer of ALTS's Left and Right
Chengsong
parents: 16
diff changeset
   615
    //we have to use r to detect the bound of nested L/Rs
Chengsong
parents: 16
diff changeset
   616
    case (v, r::Nil) => v
Chengsong
parents: 16
diff changeset
   617
    case (Right(v), r::rs) => remove(v, rs) 
15
Chengsong
parents: 14
diff changeset
   618
    case (Left(v), r::rs) => v 
17
Chengsong
parents: 16
diff changeset
   619
    //case (v, r::Nil) => v
15
Chengsong
parents: 14
diff changeset
   620
  }
16
c51178fa85fe new version of slides
Chengsong
parents: 15
diff changeset
   621
  def simple_end(v: Val): Boolean = v match {
15
Chengsong
parents: 14
diff changeset
   622
    case Left(v) => return false
Chengsong
parents: 14
diff changeset
   623
    case Right(v) => return simple_end(v)
Chengsong
parents: 14
diff changeset
   624
    case v => return true
Chengsong
parents: 14
diff changeset
   625
  }
148
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   626
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   627
  //tells if rs[i] after flatten is at the right end 
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   628
  def isend(v: Val, rs: List[ARexp], i: Int): Boolean = {//TODO: here the slice api i am not familiar with so this call might be incorrect and crash the bsimp2
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   629
    val rsbh = rs.slice(i + 1, rs.length)
15
Chengsong
parents: 14
diff changeset
   630
    val out_end = if(flats(rsbh) == Nil) true else false
Chengsong
parents: 14
diff changeset
   631
    val inner_end = simple_end(v)
Chengsong
parents: 14
diff changeset
   632
    inner_end && out_end
Chengsong
parents: 14
diff changeset
   633
  }
148
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   634
  //get the coat of v and wears it on vs
16
c51178fa85fe new version of slides
Chengsong
parents: 15
diff changeset
   635
  def get_coat(v: Val, rs: List[Rexp], vs: Val): Val = (v, rs) match{//the dual operation of remove(so-called by myself)
15
Chengsong
parents: 14
diff changeset
   636
    case (Right(v), r::Nil) => Right(vs)
Chengsong
parents: 14
diff changeset
   637
    case (Left(v), r::rs) => Left(vs) 
Chengsong
parents: 14
diff changeset
   638
    case (Right(v), r::rs) => Right(get_coat(v, rs, vs))
Chengsong
parents: 14
diff changeset
   639
  }
148
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   640
  //coat does the job of "coating" a value
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   641
  //given the number of right outside it
15
Chengsong
parents: 14
diff changeset
   642
  def coat(v: Val, i: Int) : Val = i match {
Chengsong
parents: 14
diff changeset
   643
    case 0 => v
Chengsong
parents: 14
diff changeset
   644
    case i => coat(Right(v), i - 1)
Chengsong
parents: 14
diff changeset
   645
  }
148
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   646
  def decoat(v:Val, i: Int) : Val = i match {
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   647
    case 0 => v
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   648
    case i => v match {
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   649
      case Right(v0) => decoat(v0, i - 1)
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   650
      case _ => throw new Exception("bad args decoat")
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   651
    }
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   652
  }
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   653
  //given a regex, and a value, return the rectification function for how to rebuild the original value from the simplified value
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   654
  
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   655
  def vunsimp(r: ARexp, v: Val) : Val => Val = (r, v) match {
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   656
    case (ASEQ(bs1, r1, r2), Sequ(v1, v2)) => (bsimp2(r1, v1), bsimp2(r2, v2)) match {
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   657
        case ((AZERO, _), (_, _) )=> throw new Exception("bad arguments")
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   658
        case ((_, _), (AZERO, _)) => throw new Exception("bad arguments")
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   659
        case ((AONE(bs2), v1s) , (r2s, v2s)) => (vtails => Sequ(v1, vunsimp(r2, v2)(vtails)))  //(fuse(bs1 ++ bs2, r2s), v2s )//v2 tells how to retrieve bits in r2s, which is enough as the bits of the first part of the sequence has already been integrated to the top level of the second regx.
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   660
        case ((r1s, v1s), (r2s, v2s)) => (vsmall => vsmall match {
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   661
          case Sequ(v1small, v2small) => Sequ(vunsimp(r1, v1)(v1small), vunsimp(r2, v2)(v2small))
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   662
          case _ => {
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   663
            println(vsmall) ;
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   664
            throw new Exception("bad arguments sequ")
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   665
          }
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   666
          //(ASEQ(bs1, r1s, r2s),  Sequ(v1s, v2s))
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   667
        })
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   668
    }
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   669
    case (AALTS(bs1, rs), v) => {
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   670
      val init_ind = find_pos(v, rs)
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   671
      val rightend1 = if(init_ind + 1 == rs.length) true else false
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   672
      val inner_rectfunct = vunsimp(rs(init_ind), remove(v, rs))//remove all the outer layers of left and right in v to  match the regx rs[i]
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   673
      val vpointr = bsimp2(rs(init_ind), remove(v, rs))
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   674
      val target_vs = vpointr._2
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   675
      val target_rs = vpointr._1
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   676
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   677
      val rs_simp = rs.map(bsimp)
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   678
      val target_vs_kernel = target_rs match {
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   679
        case AALTS(bs2, rs2) => remove(target_vs, rs2)//remove the secondary layer of left and right
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   680
        case r => target_vs
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   681
      }
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   682
      val target_vs_outerlayers = target_rs match {
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   683
        case AALTS(bs2, rs2) => find_pos(target_vs, rs2)//remove the secondary layer of left and right
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   684
        case r => 0
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   685
      }
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   686
      val rightend2 = target_rs match {
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   687
        case AALTS(bs2, rs2) => if(find_pos(target_vs, rs2) == rs2.length - 1) true else false
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   688
        case r => false
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   689
      }
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   690
      val isalts = target_rs match {
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   691
        case AALTS(bs2, rs2) =>  true 
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   692
        case r => false
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   693
      }
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   694
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   695
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   696
      val flat_res = flats(rs_simp)
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   697
      val flats_shit1 = right_shift(rs_simp, init_ind)
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   698
      val flats_shift2 = find_pos_aux(target_vs, target_rs)
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   699
      val flats_shift =  flats_shit1 + flats_shift2//right_shift used to be called flats_vsimp
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   700
      val new_ind = init_ind + flats_shift
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   701
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   702
      val dist_res = distinctBy(flat_res, erase)
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   703
      val front_part = distinctBy(flat_res.slice(0, new_ind + 1), erase)
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   704
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   705
      val vdb = if(dist_res.length == front_part.length )//that means the regex we are interested in is at the end of the list
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   706
      {
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   707
        coat(target_vs_kernel, front_part.length - 1)
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   708
      }
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   709
      else{
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   710
        coat(Left(target_vs_kernel), front_part.length - 1)
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   711
      }
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   712
      if(rightend1){
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   713
        if(rightend2){
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   714
          kernel_coated: Val => 
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   715
          decoat(kernel_coated, front_part.length - 1) match {
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   716
            case Left(vk) => coat(inner_rectfunct(coat(vk, target_vs_outerlayers)), init_ind)//add clause: if rs_simp(init_ind) is an alts
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   717
            case vk => coat(inner_rectfunct(coat(vk, target_vs_outerlayers)), init_ind)
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   718
          }
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   719
        }
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   720
        else{
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   721
          kernel_coated: Val => 
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   722
          decoat(kernel_coated, front_part.length - 1) match {
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   723
            case Left(vk) => if(isalts) coat(inner_rectfunct(coat(Left(vk), target_vs_outerlayers)), init_ind) 
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   724
              else coat(inner_rectfunct(coat((vk), target_vs_outerlayers)), init_ind)//add clause: if rs_simp(init_ind) is an alts
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   725
            case vk => if(isalts) coat(inner_rectfunct(coat(Left(vk), target_vs_outerlayers)), init_ind)
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   726
              else coat(inner_rectfunct(coat((vk), target_vs_outerlayers)), init_ind)
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   727
          }
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   728
        }
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   729
      }
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   730
      else{
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   731
        if(rightend2){
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   732
          kernel_coated: Val => 
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   733
          decoat(kernel_coated, front_part.length - 1) match {
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   734
            case Left(vk) => coat(Left(inner_rectfunct(coat(vk, target_vs_outerlayers))), init_ind)//add clause: if rs_simp(init_ind) is an alts
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   735
            case vk => coat(Left(inner_rectfunct(coat(vk, target_vs_outerlayers))), init_ind)
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   736
          } 
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   737
        }
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   738
        else{
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   739
          kernel_coated: Val => 
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   740
          decoat(kernel_coated, front_part.length - 1) match {
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   741
            case Left(vk) => if(isalts) coat(Left(inner_rectfunct(coat(Left(vk), target_vs_outerlayers))), init_ind)
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   742
              else coat(Left(inner_rectfunct(coat(vk, target_vs_outerlayers))), init_ind)//add clause: if rs_simp(init_ind) is an alts
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   743
            case vk => if(isalts) coat(Left(inner_rectfunct(coat(Left(vk), target_vs_outerlayers))), init_ind)
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   744
              else coat(Left(inner_rectfunct(coat(vk, target_vs_outerlayers))), init_ind)
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   745
          }     
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   746
        }
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   747
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   748
      }
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   749
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   750
    }
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   751
    //case ASTAR(bs, r) => ASTAR(bs, bsimp(r))
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   752
    case (r, v) => (v => v)
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   753
  }
17
Chengsong
parents: 16
diff changeset
   754
  //This version takes a regex and a value, return a simplified regex and its corresponding simplified value 
Chengsong
parents: 16
diff changeset
   755
  def bsimp2(r: ARexp, v: Val): (ARexp, Val) = (r,v) match{
Chengsong
parents: 16
diff changeset
   756
    case (ASEQ(bs1, r1, r2), Sequ(v1, v2)) => (bsimp2(r1, v1), bsimp2(r2, v2)) match {
Chengsong
parents: 16
diff changeset
   757
        case ((AZERO, _), (_, _) )=> (AZERO, undefined)
Chengsong
parents: 16
diff changeset
   758
        case ((_, _), (AZERO, _)) => (AZERO, undefined)
Chengsong
parents: 16
diff changeset
   759
        case ((AONE(bs2), v1s) , (r2s, v2s)) => (fuse(bs1 ++ bs2, r2s), v2s )//v2 tells how to retrieve bits in r2s, which is enough as the bits of the first part of the sequence has already been integrated to the top level of the second regx.
Chengsong
parents: 16
diff changeset
   760
        case ((r1s, v1s), (r2s, v2s)) => (ASEQ(bs1, r1s, r2s),  Sequ(v1s, v2s))
Chengsong
parents: 16
diff changeset
   761
    }
Chengsong
parents: 16
diff changeset
   762
    case (AALTS(bs1, rs), v) => {
Chengsong
parents: 16
diff changeset
   763
      val init_ind = find_pos(v, rs)
148
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   764
      val vpointr = bsimp2(rs(init_ind), remove(v, rs))//remove all the outer layers of left and right in v to  match the regx rs[i]
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   765
      val target_sv = vpointr._2
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   766
      val target_sr = vpointr._1
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   767
17
Chengsong
parents: 16
diff changeset
   768
      val rs_simp = rs.map(bsimp)
148
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   769
      val target_vs_kernel = target_sr match {
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   770
        case AALTS(bs2, rs2) => remove(target_sv, rs2)//if rs(init_ind) after simp is also an alts, we remove the R(....L(v)) outside v
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   771
        case r => target_sv
17
Chengsong
parents: 16
diff changeset
   772
      }
Chengsong
parents: 16
diff changeset
   773
      val flat_res = flats(rs_simp)
148
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   774
      val flats_shift1 = right_shift(rs_simp, init_ind)
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   775
      val flats_base = find_pos_aux(target_sv, target_sr)
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   776
      val flats_shift =  flats_shift1 + flats_base//right_shift used to be called flats_vsimp
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   777
      val new_ind = init_ind + flats_shift
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   778
17
Chengsong
parents: 16
diff changeset
   779
      val dist_res = distinctBy(flat_res, erase)
Chengsong
parents: 16
diff changeset
   780
      val front_part = distinctBy(flat_res.slice(0, new_ind + 1), erase)
148
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   781
17
Chengsong
parents: 16
diff changeset
   782
      val vdb = if(dist_res.length == front_part.length )//that means the regex we are interested in is at the end of the list
Chengsong
parents: 16
diff changeset
   783
      {
148
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   784
        coat(target_vs_kernel, front_part.length - 1)
17
Chengsong
parents: 16
diff changeset
   785
      }
Chengsong
parents: 16
diff changeset
   786
      else{
148
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   787
        coat(Left(target_vs_kernel), front_part.length - 1)
17
Chengsong
parents: 16
diff changeset
   788
      }
Chengsong
parents: 16
diff changeset
   789
      dist_res match {
Chengsong
parents: 16
diff changeset
   790
        case Nil => (AZERO, undefined)
Chengsong
parents: 16
diff changeset
   791
        case s :: Nil => (fuse(bs1, s), vdb)
Chengsong
parents: 16
diff changeset
   792
        case rs => (AALTS(bs1, rs), vdb)
Chengsong
parents: 16
diff changeset
   793
      }
Chengsong
parents: 16
diff changeset
   794
    }
Chengsong
parents: 16
diff changeset
   795
    //case ASTAR(bs, r) => ASTAR(bs, bsimp(r))
Chengsong
parents: 16
diff changeset
   796
    case (r, v) => (r, v)  
Chengsong
parents: 16
diff changeset
   797
  }
148
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   798
  //the below are all residuals from the bsimp2 function 
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   799
        //val vs_for_coating = if(isend(vs._2, rs_simp, init_ind)||flat_res.length == 1) vs_kernel else Left(vs_kernel)
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   800
        //val vf = coat(vs_for_coating, new_ind)
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   801
      //flats2 returns a list of regex and a single v
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   802
      //now |- vf: ALTS(bs1, flat_res)
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   803
      //phase 2 transformation so that aalts(bs1, rsf) => aalts(bs, rsdb) and vf => vdb
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   804
            //val size_reduction = new_ind + 1 - front_part.length
17
Chengsong
parents: 16
diff changeset
   805
  def vsimp(r: ARexp, v: Val): Val = bsimp2(r, v)._2
Chengsong
parents: 16
diff changeset
   806
  /*This version was first intended for returning a function however a value would be simpler.
15
Chengsong
parents: 14
diff changeset
   807
  def bsimp2(r: ARexp, v: Val): (ARexp, Val => Val) = (r,v) match{
Chengsong
parents: 14
diff changeset
   808
    case (ASEQ(bs1, r1, r2), v) => (bsimp2(r1), bsimp2(r2)) match {
Chengsong
parents: 14
diff changeset
   809
        case ((AZERO, _), (_, _) )=> (AZERO, undefined)
Chengsong
parents: 14
diff changeset
   810
        case ((_, _), (AZERO, _)) => (AZERO, undefined)
Chengsong
parents: 14
diff changeset
   811
        case ((AONE(bs2), f1) , (r2s, f2)) => (fuse(bs1 ++ bs2, r2s), lambda v => v match { case Sequ(_, v) => f2(v) } )
Chengsong
parents: 14
diff changeset
   812
        case ((r1s, f1), (r2s, f2)) => (ASEQ(bs1, r1s, r2s), lambda v => v match {case Sequ(v1, v2) => Sequ(f1(v1), f2(v2))}
Chengsong
parents: 14
diff changeset
   813
    }
Chengsong
parents: 14
diff changeset
   814
    case AALTS(bs1, rs) => {
Chengsong
parents: 14
diff changeset
   815
      val init_ind = find_pos(v, rs)
Chengsong
parents: 14
diff changeset
   816
      val vs = bsimp2(rs[init_ind], remove(v, rs))//remove all the outer layers of left and right in v to  match the regx rs[i]
Chengsong
parents: 14
diff changeset
   817
      val rs_simp = rs.map(bsimp)
Chengsong
parents: 14
diff changeset
   818
      val vs_kernel = rs_simp[init_ind] match {
Chengsong
parents: 14
diff changeset
   819
        case AALTS(bs2, rs2) => remove(vs, rs_simp[init_ind])//remove the secondary layer of left and right
Chengsong
parents: 14
diff changeset
   820
        case r => vs
Chengsong
parents: 14
diff changeset
   821
      }
Chengsong
parents: 14
diff changeset
   822
      val vs_for_coating = if(isend(vs, rs_simp, init_ind)) vs_kernel else Left(vs_kernel)
Chengsong
parents: 14
diff changeset
   823
Chengsong
parents: 14
diff changeset
   824
      val r_s = rs_simp[init_ind]
148
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   825
      val shift = right_shift(vs, rs_simp, init_ind) + find_pos(vs, rs_simp[init_ind])
15
Chengsong
parents: 14
diff changeset
   826
      val vf = coat(vs_for_coating, shift + init_ind)
Chengsong
parents: 14
diff changeset
   827
Chengsong
parents: 14
diff changeset
   828
      val flat_res = flats(rs_simp)//flats2 returns a list of regex and a single v
Chengsong
parents: 14
diff changeset
   829
      val dist_res = distinctBy(flat_res, erase)
Chengsong
parents: 14
diff changeset
   830
      dist_res match {
Chengsong
parents: 14
diff changeset
   831
        case Nil => AZERO
Chengsong
parents: 14
diff changeset
   832
        case s :: Nil => fuse(bs1, s)
Chengsong
parents: 14
diff changeset
   833
        case rs => AALTS(bs1, rs)  
Chengsong
parents: 14
diff changeset
   834
      }
Chengsong
parents: 14
diff changeset
   835
    }
Chengsong
parents: 14
diff changeset
   836
    //case ASTAR(bs, r) => ASTAR(bs, bsimp(r))
Chengsong
parents: 14
diff changeset
   837
    case r => r  
16
c51178fa85fe new version of slides
Chengsong
parents: 15
diff changeset
   838
  }*/
5
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   839
  def super_bsimp(r: ARexp): ARexp = r match {
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   840
    case ASEQ(bs1, r1, r2) => (super_bsimp(r1), super_bsimp(r2)) match {
0
Chengsong
parents:
diff changeset
   841
        case (AZERO, _) => AZERO
Chengsong
parents:
diff changeset
   842
        case (_, AZERO) => AZERO
11
9c1ca6d6e190 The C(Char) construct is incompatible with the code and retrieve in Fahad's thesis.
Chengsong
parents: 5
diff changeset
   843
        case (AONE(bs2), r2s) => fuse(bs1 ++ bs2, r2s)//万一是(r1, alts(rs))这种形式呢
9c1ca6d6e190 The C(Char) construct is incompatible with the code and retrieve in Fahad's thesis.
Chengsong
parents: 5
diff changeset
   844
        case (AALTS(bs2, rs), r2) => AALTS(bs1 ++ bs2, rs.map(r => r match {case AONE(bs3) => fuse(bs3, r2) case r => ASEQ(Nil, r, r2)} ) ) 
0
Chengsong
parents:
diff changeset
   845
        case (r1s, r2s) => ASEQ(bs1, r1s, r2s)
Chengsong
parents:
diff changeset
   846
    }
Chengsong
parents:
diff changeset
   847
    case AALTS(bs1, rs) => {
5
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   848
      val rs_simp = rs.map(super_bsimp)
0
Chengsong
parents:
diff changeset
   849
      val flat_res = flats(rs_simp)
Chengsong
parents:
diff changeset
   850
      val dist_res = distinctBy(flat_res, erase)
Chengsong
parents:
diff changeset
   851
      dist_res match {
Chengsong
parents:
diff changeset
   852
        case Nil => AZERO
Chengsong
parents:
diff changeset
   853
        case s :: Nil => fuse(bs1, s)
Chengsong
parents:
diff changeset
   854
        case rs => AALTS(bs1, rs)  
Chengsong
parents:
diff changeset
   855
      }
Chengsong
parents:
diff changeset
   856
    }
5
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   857
    //case ASTAR(bs, r) => ASTAR(bs, bsimp(r))
0
Chengsong
parents:
diff changeset
   858
    case r => r
Chengsong
parents:
diff changeset
   859
  }
Chengsong
parents:
diff changeset
   860
5
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   861
0
Chengsong
parents:
diff changeset
   862
  def simp_weakened(r: Rexp): Rexp = r match {
Chengsong
parents:
diff changeset
   863
    case SEQ(r1, r2) => (simp_weakened(r1), r2) match {
Chengsong
parents:
diff changeset
   864
        case (ZERO, _) => ZERO
Chengsong
parents:
diff changeset
   865
        case (_, ZERO) => ZERO
Chengsong
parents:
diff changeset
   866
        case (ONE, r2s) => r2s
Chengsong
parents:
diff changeset
   867
        case (r1s, r2s) => SEQ(r1s, r2s)
Chengsong
parents:
diff changeset
   868
    }
Chengsong
parents:
diff changeset
   869
    case ALTS(rs) => {
Chengsong
parents:
diff changeset
   870
      val rs_simp = rs.map(simp_weakened)
Chengsong
parents:
diff changeset
   871
      val flat_res = rflats(rs_simp)
Chengsong
parents:
diff changeset
   872
      val dist_res = rs_simp.distinct
Chengsong
parents:
diff changeset
   873
      dist_res match {
Chengsong
parents:
diff changeset
   874
        case Nil => ZERO
Chengsong
parents:
diff changeset
   875
        case s :: Nil => s
Chengsong
parents:
diff changeset
   876
        case rs => ALTS(rs)  
Chengsong
parents:
diff changeset
   877
      }
Chengsong
parents:
diff changeset
   878
    }
Chengsong
parents:
diff changeset
   879
    case STAR(r) => STAR(simp_weakened(r))
Chengsong
parents:
diff changeset
   880
    case r => r
Chengsong
parents:
diff changeset
   881
  }
Chengsong
parents:
diff changeset
   882
    
Chengsong
parents:
diff changeset
   883
  def bders_simp (s: List[Char], r: ARexp) : ARexp = s match {
Chengsong
parents:
diff changeset
   884
    case Nil => r
Chengsong
parents:
diff changeset
   885
    case c::s => bders_simp(s, bsimp(bder(c, r)))
Chengsong
parents:
diff changeset
   886
  }
107
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   887
  def bders_simp_rf (s: List[Char], r: ARexp) : ARexp = s match {
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   888
    case Nil => r
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   889
    case c::s => bders_simp_rf(s, bsimp_rf(bder(c, r)))
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   890
  }
b1e365afa29c changes
Chengsong
parents: 93
diff changeset
   891
  
14
610f14009c0b the property
Chengsong
parents: 12
diff changeset
   892
  //----------------------------------------------------------------------------experiment bsimp
610f14009c0b the property
Chengsong
parents: 12
diff changeset
   893
  /*
610f14009c0b the property
Chengsong
parents: 12
diff changeset
   894
0
Chengsong
parents:
diff changeset
   895
  */
Chengsong
parents:
diff changeset
   896
  /*
Chengsong
parents:
diff changeset
   897
  def time[T](code: => T) = {
Chengsong
parents:
diff changeset
   898
    val start = System.nanoTime()
Chengsong
parents:
diff changeset
   899
    val result = code
Chengsong
parents:
diff changeset
   900
    val end = System.nanoTime()
Chengsong
parents:
diff changeset
   901
    println((end - start)/1.0e9)
Chengsong
parents:
diff changeset
   902
    result
Chengsong
parents:
diff changeset
   903
  }
Chengsong
parents:
diff changeset
   904
  */
Chengsong
parents:
diff changeset
   905
  // main unsimplified lexing function (produces a value)
148
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   906
  def blex(s: List[Char], r: ARexp) : Bits = s match {
0
Chengsong
parents:
diff changeset
   907
    case Nil => if (bnullable(r)) mkepsBC(r) else throw new Exception("Not matched")
Chengsong
parents:
diff changeset
   908
    case c::cs => {
Chengsong
parents:
diff changeset
   909
      val der_res = bder(c,r)
148
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   910
      blex(cs, der_res)
0
Chengsong
parents:
diff changeset
   911
    }
Chengsong
parents:
diff changeset
   912
  }
Chengsong
parents:
diff changeset
   913
148
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   914
  def bpre_lexing(r: Rexp, s: String) = blex( s.toList, internalise(r) )
c8ef391dd6f7 vunsimp
Chengsong
parents: 109
diff changeset
   915
  def blexing(s: String, r: Rexp) : Val = decode(r, blex( s.toList, internalise(r) ) )
0
Chengsong
parents:
diff changeset
   916
Chengsong
parents:
diff changeset
   917
  var bder_time = 0L
Chengsong
parents:
diff changeset
   918
  var bsimp_time = 0L
Chengsong
parents:
diff changeset
   919
  var mkepsBC_time = 0L
Chengsong
parents:
diff changeset
   920
  var small_de = 2
Chengsong
parents:
diff changeset
   921
  var big_de = 5
Chengsong
parents:
diff changeset
   922
  var usual_de = 3
Chengsong
parents:
diff changeset
   923
  
Chengsong
parents:
diff changeset
   924
  def blex_simp(r: ARexp, s: List[Char]) : Bits = s match {
Chengsong
parents:
diff changeset
   925
    case Nil => {
Chengsong
parents:
diff changeset
   926
      if (bnullable(r)) {
Chengsong
parents:
diff changeset
   927
        //println(asize(r))
5
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   928
        mkepsBC(r)
0
Chengsong
parents:
diff changeset
   929
      }
Chengsong
parents:
diff changeset
   930
    else throw new Exception("Not matched")
Chengsong
parents:
diff changeset
   931
    }
Chengsong
parents:
diff changeset
   932
    case c::cs => {
Chengsong
parents:
diff changeset
   933
      val der_res = bder(c,r)
Chengsong
parents:
diff changeset
   934
      val simp_res = bsimp(der_res)
Chengsong
parents:
diff changeset
   935
      blex_simp(simp_res, cs)      
Chengsong
parents:
diff changeset
   936
    }
Chengsong
parents:
diff changeset
   937
  }
5
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   938
  def super_blex_simp(r: ARexp, s: List[Char]): Bits = s match {
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   939
    case Nil => {
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   940
      if (bnullable(r)) {
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   941
        mkepsBC(r)
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   942
      }
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   943
      else throw new Exception("Not matched")
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   944
    }
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   945
    case c::cs => {
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   946
      super_blex_simp(super_bsimp(bder(c,r)), cs)
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   947
    }
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   948
  }
0
Chengsong
parents:
diff changeset
   949
  def blex_real_simp(r: ARexp, s: List[Char]): ARexp = s match{
Chengsong
parents:
diff changeset
   950
    case Nil => r
Chengsong
parents:
diff changeset
   951
    case c::cs => blex_real_simp(bsimp(bder(c, r)), cs)
Chengsong
parents:
diff changeset
   952
  }
Chengsong
parents:
diff changeset
   953
Chengsong
parents:
diff changeset
   954
Chengsong
parents:
diff changeset
   955
  //size: of a Aregx for testing purposes 
Chengsong
parents:
diff changeset
   956
  def size(r: Rexp) : Int = r match {
Chengsong
parents:
diff changeset
   957
    case ZERO => 1
Chengsong
parents:
diff changeset
   958
    case ONE => 1
Chengsong
parents:
diff changeset
   959
    case CHAR(_) => 1
Chengsong
parents:
diff changeset
   960
    case SEQ(r1, r2) => 1 + size(r1) + size(r2)
Chengsong
parents:
diff changeset
   961
    case ALTS(rs) => 1 + rs.map(size).sum
Chengsong
parents:
diff changeset
   962
    case STAR(r) => 1 + size(r)
Chengsong
parents:
diff changeset
   963
  }
Chengsong
parents:
diff changeset
   964
Chengsong
parents:
diff changeset
   965
  def asize(a: ARexp) = size(erase(a))
Chengsong
parents:
diff changeset
   966
Chengsong
parents:
diff changeset
   967
Chengsong
parents:
diff changeset
   968
  // decoding does not work yet
Chengsong
parents:
diff changeset
   969
  def blexing_simp(r: Rexp, s: String) = {
Chengsong
parents:
diff changeset
   970
    val bit_code = blex_simp(internalise(r), s.toList)
5
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   971
    decode(r, bit_code) 
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   972
  }
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   973
  def super_blexing_simp(r: Rexp, s: String) = {
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
   974
    decode(r, super_blex_simp(internalise(r), s.toList))
0
Chengsong
parents:
diff changeset
   975
  }
Chengsong
parents:
diff changeset
   976
Chengsong
parents:
diff changeset
   977
Chengsong
parents:
diff changeset
   978
Chengsong
parents:
diff changeset
   979
Chengsong
parents:
diff changeset
   980
Chengsong
parents:
diff changeset
   981
  // Lexing Rules for a Small While Language
Chengsong
parents:
diff changeset
   982
Chengsong
parents:
diff changeset
   983
  //symbols
Chengsong
parents:
diff changeset
   984
  /*
Chengsong
parents:
diff changeset
   985
  val SYM = PRED("abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ".contains(_))
Chengsong
parents:
diff changeset
   986
  
Chengsong
parents:
diff changeset
   987
  //digits
Chengsong
parents:
diff changeset
   988
  val DIGIT = PRED("0123456789".contains(_))
Chengsong
parents:
diff changeset
   989
  //identifiers
Chengsong
parents:
diff changeset
   990
  val ID = SYM ~ (SYM | DIGIT).% 
Chengsong
parents:
diff changeset
   991
  //numbers
Chengsong
parents:
diff changeset
   992
  val NUM = STAR(DIGIT)
Chengsong
parents:
diff changeset
   993
  //keywords
Chengsong
parents:
diff changeset
   994
  val KEYWORD : Rexp = "skip" | "while" | "do" | "if" | "then" | "else" | "read" | "write" | "true" | "false"
Chengsong
parents:
diff changeset
   995
  val AKEYWORD: Rexp = ALTS(List("skip" , "while" , "do" , "if" , "then" , "else" , "read" , "write" , "true" , "false"))
Chengsong
parents:
diff changeset
   996
  //semicolons
Chengsong
parents:
diff changeset
   997
  val SEMI: Rexp = ";"
Chengsong
parents:
diff changeset
   998
  //operators
Chengsong
parents:
diff changeset
   999
  val OP: Rexp = ":=" | "==" | "-" | "+" | "*" | "!=" | "<" | ">" | "<=" | ">=" | "%" | "/"
Chengsong
parents:
diff changeset
  1000
  val AOP: Rexp = ALTS(List(":=" , "==" , "-" , "+" , "*" , "!=" , "<" , ">" , "<=" , ">=" , "%" , "/"))
Chengsong
parents:
diff changeset
  1001
  //whitespaces
Chengsong
parents:
diff changeset
  1002
  val WHITESPACE = PLUS(" " | "\n" | "\t")
Chengsong
parents:
diff changeset
  1003
  //parentheses
Chengsong
parents:
diff changeset
  1004
  val RPAREN: Rexp = ")"
Chengsong
parents:
diff changeset
  1005
  val LPAREN: Rexp = "("
Chengsong
parents:
diff changeset
  1006
  val BEGIN: Rexp = "{"
Chengsong
parents:
diff changeset
  1007
  val END: Rexp = "}"
Chengsong
parents:
diff changeset
  1008
  //strings...but probably needs not
Chengsong
parents:
diff changeset
  1009
  val STRING: Rexp = "\"" ~ SYM.% ~ "\""
Chengsong
parents:
diff changeset
  1010
Chengsong
parents:
diff changeset
  1011
Chengsong
parents:
diff changeset
  1012
Chengsong
parents:
diff changeset
  1013
  val WHILE_REGS = (("k" $ KEYWORD) | 
Chengsong
parents:
diff changeset
  1014
                    ("i" $ ID) | 
Chengsong
parents:
diff changeset
  1015
                    ("o" $ OP) | 
Chengsong
parents:
diff changeset
  1016
                    ("n" $ NUM) | 
Chengsong
parents:
diff changeset
  1017
                    ("s" $ SEMI) | 
Chengsong
parents:
diff changeset
  1018
                    ("str" $ STRING) |
Chengsong
parents:
diff changeset
  1019
                    ("p" $ (LPAREN | RPAREN)) | 
Chengsong
parents:
diff changeset
  1020
                    ("b" $ (BEGIN | END)) | 
Chengsong
parents:
diff changeset
  1021
                    ("w" $ WHITESPACE)).%
Chengsong
parents:
diff changeset
  1022
Chengsong
parents:
diff changeset
  1023
  val AWHILE_REGS = (
Chengsong
parents:
diff changeset
  1024
    ALTS(
Chengsong
parents:
diff changeset
  1025
      List(
Chengsong
parents:
diff changeset
  1026
        ("k" $ AKEYWORD), 
Chengsong
parents:
diff changeset
  1027
                    ("i" $ ID),
Chengsong
parents:
diff changeset
  1028
                    ("o" $ AOP) , 
Chengsong
parents:
diff changeset
  1029
                    ("n" $ NUM) ,
Chengsong
parents:
diff changeset
  1030
                    ("s" $ SEMI) ,
Chengsong
parents:
diff changeset
  1031
                    ("str" $ STRING), 
Chengsong
parents:
diff changeset
  1032
                    ("p" $ (LPAREN | RPAREN)), 
Chengsong
parents:
diff changeset
  1033
                    ("b" $ (BEGIN | END)), 
Chengsong
parents:
diff changeset
  1034
                    ("w" $ WHITESPACE)
Chengsong
parents:
diff changeset
  1035
      )
Chengsong
parents:
diff changeset
  1036
    )
Chengsong
parents:
diff changeset
  1037
  ).%
Chengsong
parents:
diff changeset
  1038
Chengsong
parents:
diff changeset
  1039
*/
Chengsong
parents:
diff changeset
  1040
Chengsong
parents:
diff changeset
  1041
Chengsong
parents:
diff changeset
  1042
  //--------------------------------------------------------------------------------------------------------START OF NON-BITCODE PART (TESTING)
Chengsong
parents:
diff changeset
  1043
  /*
Chengsong
parents:
diff changeset
  1044
  // Two Simple While programs
Chengsong
parents:
diff changeset
  1045
  //========================
Chengsong
parents:
diff changeset
  1046
  println("prog0 test")
Chengsong
parents:
diff changeset
  1047
Chengsong
parents:
diff changeset
  1048
  val prog0 = """read n"""
Chengsong
parents:
diff changeset
  1049
  println(env(lexing_simp(WHILE_REGS, prog0)))
Chengsong
parents:
diff changeset
  1050
  println(tokenise(WHILE_REGS, prog0))
Chengsong
parents:
diff changeset
  1051
Chengsong
parents:
diff changeset
  1052
  println("prog1 test")
Chengsong
parents:
diff changeset
  1053
Chengsong
parents:
diff changeset
  1054
  val prog1 = """read  n; write (n)"""
Chengsong
parents:
diff changeset
  1055
  println(tokenise(WHILE_REGS, prog1))
Chengsong
parents:
diff changeset
  1056
Chengsong
parents:
diff changeset
  1057
  */
Chengsong
parents:
diff changeset
  1058
  // Bigger Tests
Chengsong
parents:
diff changeset
  1059
  //==============
Chengsong
parents:
diff changeset
  1060
Chengsong
parents:
diff changeset
  1061
  def escape(raw: String): String = {
Chengsong
parents:
diff changeset
  1062
    import scala.reflect.runtime.universe._
Chengsong
parents:
diff changeset
  1063
    Literal(Constant(raw)).toString
Chengsong
parents:
diff changeset
  1064
  }
Chengsong
parents:
diff changeset
  1065
Chengsong
parents:
diff changeset
  1066
  val prog2 = """
Chengsong
parents:
diff changeset
  1067
  write "Fib";
Chengsong
parents:
diff changeset
  1068
  read n;
Chengsong
parents:
diff changeset
  1069
  minus1 := 0;
Chengsong
parents:
diff changeset
  1070
  minus2 := 1;
Chengsong
parents:
diff changeset
  1071
  while n > 0 do {
Chengsong
parents:
diff changeset
  1072
    temp := minus2;
Chengsong
parents:
diff changeset
  1073
    minus2 := minus1 + minus2;
Chengsong
parents:
diff changeset
  1074
    minus1 := temp;
Chengsong
parents:
diff changeset
  1075
    n := n - 1
Chengsong
parents:
diff changeset
  1076
  };
Chengsong
parents:
diff changeset
  1077
  write "Result";
Chengsong
parents:
diff changeset
  1078
  write minus2
Chengsong
parents:
diff changeset
  1079
  """
Chengsong
parents:
diff changeset
  1080
Chengsong
parents:
diff changeset
  1081
  val prog3 = """
Chengsong
parents:
diff changeset
  1082
  start := 1000;
Chengsong
parents:
diff changeset
  1083
  x := start;
Chengsong
parents:
diff changeset
  1084
  y := start;
Chengsong
parents:
diff changeset
  1085
  z := start;
Chengsong
parents:
diff changeset
  1086
  while 0 < x do {
Chengsong
parents:
diff changeset
  1087
  while 0 < y do {
Chengsong
parents:
diff changeset
  1088
    while 0 < z do {
Chengsong
parents:
diff changeset
  1089
      z := z - 1
Chengsong
parents:
diff changeset
  1090
    };
Chengsong
parents:
diff changeset
  1091
    z := start;
Chengsong
parents:
diff changeset
  1092
    y := y - 1
Chengsong
parents:
diff changeset
  1093
  };     
Chengsong
parents:
diff changeset
  1094
  y := start;
Chengsong
parents:
diff changeset
  1095
  x := x - 1
Chengsong
parents:
diff changeset
  1096
  }
Chengsong
parents:
diff changeset
  1097
  """
Chengsong
parents:
diff changeset
  1098
  /*
Chengsong
parents:
diff changeset
  1099
  for(i <- 400 to 400 by 1){
Chengsong
parents:
diff changeset
  1100
    println(i+":")
Chengsong
parents:
diff changeset
  1101
    blexing_simp(WHILE_REGS, prog2 * i)
Chengsong
parents:
diff changeset
  1102
  } */
Chengsong
parents:
diff changeset
  1103
Chengsong
parents:
diff changeset
  1104
    /*
Chengsong
parents:
diff changeset
  1105
    for (i <- 2 to 5){
Chengsong
parents:
diff changeset
  1106
      for(j <- 1 to 3){
Chengsong
parents:
diff changeset
  1107
        println(i,j)
Chengsong
parents:
diff changeset
  1108
        small_de = i
Chengsong
parents:
diff changeset
  1109
        usual_de = i + j
Chengsong
parents:
diff changeset
  1110
        big_de = i + 2*j 
Chengsong
parents:
diff changeset
  1111
        blexing_simp(AWHILE_REGS, prog2 * 100)
Chengsong
parents:
diff changeset
  1112
      }
Chengsong
parents:
diff changeset
  1113
    }*/
Chengsong
parents:
diff changeset
  1114
Chengsong
parents:
diff changeset
  1115
  /*
Chengsong
parents:
diff changeset
  1116
  println("Tokens of prog2")
Chengsong
parents:
diff changeset
  1117
  println(tokenise(WHILE_REGS, prog2).mkString("\n"))
Chengsong
parents:
diff changeset
  1118
Chengsong
parents:
diff changeset
  1119
  val fib_tokens = tokenise(WHILE_REGS, prog2)
Chengsong
parents:
diff changeset
  1120
  fib_tokens.map{case (s1, s2) => (escape(s1), escape(s2))}.mkString(",\n")
Chengsong
parents:
diff changeset
  1121
Chengsong
parents:
diff changeset
  1122
Chengsong
parents:
diff changeset
  1123
  val test_tokens = tokenise(WHILE_REGS, prog3)
Chengsong
parents:
diff changeset
  1124
  test_tokens.map{case (s1, s2) => (escape(s1), escape(s2))}.mkString(",\n")
Chengsong
parents:
diff changeset
  1125
  */
Chengsong
parents:
diff changeset
  1126
Chengsong
parents:
diff changeset
  1127
  /*
Chengsong
parents:
diff changeset
  1128
  println("time test for blexing_simp")
Chengsong
parents:
diff changeset
  1129
  for (i <- 1 to 1 by 1) {
Chengsong
parents:
diff changeset
  1130
    lexing_simp(WHILE_REGS, prog2 * i)
Chengsong
parents:
diff changeset
  1131
    blexing_simp(WHILE_REGS, prog2 * i)
Chengsong
parents:
diff changeset
  1132
    for( j <- 0 to each_simp_timeb.length - 1){
Chengsong
parents:
diff changeset
  1133
      if( each_simp_timeb(j)/each_simp_time(j) >= 10.0 )
Chengsong
parents:
diff changeset
  1134
        println(j, each_simp_timeb(j), each_simp_time(j))
Chengsong
parents:
diff changeset
  1135
    }
Chengsong
parents:
diff changeset
  1136
  }
Chengsong
parents:
diff changeset
  1137
  */
Chengsong
parents:
diff changeset
  1138
Chengsong
parents:
diff changeset
  1139
Chengsong
parents:
diff changeset
  1140
  //--------------------------------------------------------------------------------------------------------END OF NON-BITCODE PART (TESTING)
Chengsong
parents:
diff changeset
  1141
Chengsong
parents:
diff changeset
  1142
Chengsong
parents:
diff changeset
  1143
Chengsong
parents:
diff changeset
  1144
  def clear() = {
Chengsong
parents:
diff changeset
  1145
    print("")
Chengsong
parents:
diff changeset
  1146
    //print("\33[H\33[2J")
Chengsong
parents:
diff changeset
  1147
  }
Chengsong
parents:
diff changeset
  1148
Chengsong
parents:
diff changeset
  1149
  //testing the two lexings produce the same value
Chengsong
parents:
diff changeset
  1150
  //enumerates strings of length n over alphabet cs
Chengsong
parents:
diff changeset
  1151
  def strs(n: Int, cs: String) : Set[String] = {
Chengsong
parents:
diff changeset
  1152
    if (n == 0) Set("")
Chengsong
parents:
diff changeset
  1153
    else {
Chengsong
parents:
diff changeset
  1154
      val ss = strs(n - 1, cs)
Chengsong
parents:
diff changeset
  1155
      ss ++
Chengsong
parents:
diff changeset
  1156
      (for (s <- ss; c <- cs.toList) yield c + s)
Chengsong
parents:
diff changeset
  1157
    }
Chengsong
parents:
diff changeset
  1158
  }
Chengsong
parents:
diff changeset
  1159
  def enum(n: Int, s: String) : Stream[Rexp] = n match {
Chengsong
parents:
diff changeset
  1160
    case 0 => ZERO #:: ONE #:: s.toStream.map(CHAR)
Chengsong
parents:
diff changeset
  1161
    case n => {  
Chengsong
parents:
diff changeset
  1162
      val rs = enum(n - 1, s)
Chengsong
parents:
diff changeset
  1163
      rs #:::
Chengsong
parents:
diff changeset
  1164
      (for (r1 <- rs; r2 <- rs) yield ALT(r1, r2)) #:::
Chengsong
parents:
diff changeset
  1165
      (for (r1 <- rs; r2 <- rs) yield SEQ(r1, r2)) #:::
Chengsong
parents:
diff changeset
  1166
      (for (r1 <- rs) yield STAR(r1))
Chengsong
parents:
diff changeset
  1167
    }
Chengsong
parents:
diff changeset
  1168
  }
Chengsong
parents:
diff changeset
  1169
Chengsong
parents:
diff changeset
  1170
  //tests blexing and lexing
Chengsong
parents:
diff changeset
  1171
  def tests_blexer_simp(ss: Set[String])(r: Rexp) = {
Chengsong
parents:
diff changeset
  1172
    clear()
Chengsong
parents:
diff changeset
  1173
    //println(s"Testing ${r}")
Chengsong
parents:
diff changeset
  1174
    for (s <- ss.par) yield {
Chengsong
parents:
diff changeset
  1175
      val res1 = Try(Some(lexing_simp(r, s))).getOrElse(None)
5
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
  1176
      val res2 = Try(Some(super_blexing_simp(r, s))).getOrElse(None)
0
Chengsong
parents:
diff changeset
  1177
      if (res1 != res2) println(s"Disagree on ${r} and ${s}")
Chengsong
parents:
diff changeset
  1178
      if (res1 != res2) println(s"   ${res1} !=  ${res2}")
Chengsong
parents:
diff changeset
  1179
      if (res1 != res2) Some((r, s)) else None
Chengsong
parents:
diff changeset
  1180
    }
Chengsong
parents:
diff changeset
  1181
  }
Chengsong
parents:
diff changeset
  1182
Chengsong
parents:
diff changeset
  1183
Chengsong
parents:
diff changeset
  1184
5
622ddbb1223a correctness test with enumeration
Chengsong
parents: 3
diff changeset
  1185
  
0
Chengsong
parents:
diff changeset
  1186
  /*
Chengsong
parents:
diff changeset
  1187
  def single_expression_explorer(ar: ARexp, ss: Set[String]): Unit = {
Chengsong
parents:
diff changeset
  1188
    for (s <- ss){
Chengsong
parents:
diff changeset
  1189
      
Chengsong
parents:
diff changeset
  1190
      val der_res = bder(c, ar) 
Chengsong
parents:
diff changeset
  1191
      val simp_res = bsimp(der_res)
Chengsong
parents:
diff changeset
  1192
      println(asize(der_res))
Chengsong
parents:
diff changeset
  1193
      println(asize(simp_res))
Chengsong
parents:
diff changeset
  1194
      single_expression_explorer(simp_res, (sc - c))
Chengsong
parents:
diff changeset
  1195
    }
Chengsong
parents:
diff changeset
  1196
  }*/
Chengsong
parents:
diff changeset
  1197
Chengsong
parents:
diff changeset
  1198
  //single_expression_explorer(internalise(("c"~("a"+"b"))%) , Set('a','b','c'))
Chengsong
parents:
diff changeset
  1199
Chengsong
parents:
diff changeset
  1200
Chengsong
parents:
diff changeset
  1201
}
Chengsong
parents:
diff changeset
  1202
Chengsong
parents:
diff changeset
  1203
import Rexp.Bits
Chengsong
parents:
diff changeset
  1204
abstract class ARexp 
Chengsong
parents:
diff changeset
  1205
case object AZERO extends ARexp
Chengsong
parents:
diff changeset
  1206
case class AONE(bs: Bits) extends ARexp
Chengsong
parents:
diff changeset
  1207
case class ACHAR(bs: Bits, f: Char) extends ARexp
Chengsong
parents:
diff changeset
  1208
case class AALTS(bs: Bits, rs: List[ARexp]) extends ARexp 
Chengsong
parents:
diff changeset
  1209
case class ASEQ(bs: Bits, r1: ARexp, r2: ARexp) extends ARexp 
Chengsong
parents:
diff changeset
  1210
case class ASTAR(bs: Bits, r: ARexp) extends ARexp 
Chengsong
parents:
diff changeset
  1211
Chengsong
parents:
diff changeset
  1212
Chengsong
parents:
diff changeset
  1213
Chengsong
parents:
diff changeset
  1214
abstract class Val
Chengsong
parents:
diff changeset
  1215
case object Empty extends Val
Chengsong
parents:
diff changeset
  1216
case class Chr(c: Char) extends Val
Chengsong
parents:
diff changeset
  1217
case class Sequ(v1: Val, v2: Val) extends Val
Chengsong
parents:
diff changeset
  1218
case class Left(v: Val) extends Val
Chengsong
parents:
diff changeset
  1219
case class Right(v: Val) extends Val
Chengsong
parents:
diff changeset
  1220
case class Stars(vs: List[Val]) extends Val
Chengsong
parents:
diff changeset
  1221
case class Rec(x: String, v: Val) extends Val
17
Chengsong
parents: 16
diff changeset
  1222
case object undefined extends Val
0
Chengsong
parents:
diff changeset
  1223
//case class Pos(i: Int, v: Val) extends Val
Chengsong
parents:
diff changeset
  1224
case object Prd extends Val